Method and apparatus for parallelly processing data and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S772000, C714S763000

Reexamination Certificate

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10842568

ABSTRACT:
A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcting the first data according to the first syndrome, while reading the second data, and calculating the second syndrome based on the second data and the second ECC code, (3) and correcting the second data according to the second syndrome, while reading the third data and calculating the third syndrome based on the third data and the third ECC code.

REFERENCES:
patent: 5056010 (1991-10-01), Huang
patent: 5138620 (1992-08-01), Miyazaki
patent: 5257391 (1993-10-01), DuLac et al.
patent: 6332206 (2001-12-01), Nakatsuji et al.
patent: 6986095 (2006-01-01), Maeda et al.

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