Method and apparatus for optimizing the performance of LDxL and

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711145, 711156, 711163, G06F 1300

Patent

active

061417343

ABSTRACT:
A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands.

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