4. Electrical computers and digital processing systems: processing
  5. Processing architecture
  6. Long instruction word

David Arthur James Webb, Jr.

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Data cache having store queue bypass for out-of-order...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate

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Method and apparatus for determining availability of a queue...

Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate

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Method and apparatus for determining availability of a queue...

Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate

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Method and apparatus for employing a cycle bit parallel executin

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
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Method and apparatus for maximizing utilization of an internal p

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Profile ID: LFUS-PAI-P-1644887

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