Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-04
2002-09-24
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C710S120000, C714S025000
Reexamination Certificate
active
06457150
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to testing and debugging of integrated circuits and, in particular, to on-chip systems for monitoring circuit nodes within the circuits.
BACKGROUND OF THE INVENTION
Application-Specific Integrated Circuits or ASICs are chips that contain an array of hardware logic devices that are programmed by a system designer to produce a specific behavior. ASICs have been used for years as a way of providing connection or “glue” logic in a single device on a board, but more recently they have been used to provide the logic for an entire board design on a single chip. This type of circuit design is commonly called a “system on a chip.” Even more recently, processors have been included in these designs. Many popular standard CPU architectures such as “ARM” and “MIPS” are available in hardware description language libraries which allows these architectures to be integrated with memory and I/O devices on a single chip to create a custom implementation for a particular application.
The advantage of this approach is a lower overall cost for systems that are produced in relatively high volumes. In addition, system quality is better because there are fewer interconnections between chips on a board, which interconnections are prone to failure. System speed is also much higher because the signal paths within a chip are much shorter than those between chips.
The problem with such complex ASICs is that they are difficult to test and debug because many address and data signals, which are required by many conventional debugging tools and logic analyzers, are not available outside of the chip. One prior art solution is to include software in the chip that allows debug operations to be performed in conjunction with an external debugging system. The problem with this approach is that additional memory is required on the chip to store the debugging software, which memory is only used during a debugging process and, thus drives up the overall cost of the system. Another alternative is to build the debugging software into the design of the CPU itself in the form of a set of microcoded instructions. This alternative has the advantage of always being available to the system, so that problems encountered after the system has been deployed in the field can be debugged in the field. The problem with this approach is that it precludes use of ASIC designs that use CPUs created with popular ARM or MIPS architectures that do not incorporate the debugging instructions. Another option is JTAG technology which uses a 4-pin interface that implements control signals and a bidirectional serial data path. JTAG allows access to registers defined within a chip, and with the proper support built into a chip, the interface can be used to download and execute code, and to examine register and memory values. The problem with such a system is that it lacks real-time trace access to internal system nodes and therefore, some problems, such as timing problems are difficult to detect and correct.
Consequently, another prior art approach has been to equip the ASIC chip with internal hardware which collects internal circuit node data and conveys the debug data externally through a debugging port. However, I/O devices on the ASIC chip often require dedicated pins on the ASIC chip and quickly exhaust the available pins, leaving no room for a parallel debug data path. One method for dealing with this problem is to use a serial interface which requires only a few dedicated pins. With such an interface, a burst of data that exceeds the data transfer rate of the port must either be buffered or lost.
Another prior art solution is to place a data selector onto the ASIC chip which can selectively connect internal integrated circuit nodes to the debugging port allowing a direct trace to be performed on a selected node. An example of such a device is a DW_debugger circuit whose design is generated and licensed by Snopsys, Inc. located at Mountainview, Calif. This circuit includes an internal UART and ASCII engine which will accept a serial stream of bits on a two wire RS232 port, interpret the bits stream as a command plus an address. The command controls a multiplexer which connects a selected multiplexer input to a two wire data port. Each of the multiplexer inputs is connected to an internal circuit node that the ASIC designer wants to monitor.
Although such a device provides a trace path to selected internal circuit points, it requires that each of the selected internal circuit points be connected to the multiplexer by a dedicated wire run. In a complicated ASIC, it may be necessary to monitor hundreds or thousands of discrete points, resulting in hundreds or thousands of wire runs to the location of the multiplexer. These wire runs can greatly impact the physical design of the ASIC chip by limiting the placement of the ASIC functional elements and the routing of the connections, often increasing wire delays . In addition, the large number of wire runs causes severe wire congestion, which, in turn, can seriously hamper timing closure and ultimately increase the time needed to design the circuit.
Therefore, there is a need for a monitoring circuit which can provide direct access to selected nodes in the ASIC and which does not greatly affect ASIC element design and placement and which reduces wire congestion.
SUMMARY OF THE INVENTION
In accordance with one illustrative embodiment of the invention, an on-chip monitoring circuit is composed of a plurality of addressable nodes that are connected together in a circuit which extends from an external data port to each of the monitored circuit points. Address and enable information is passed from node to node. Each node contains address decoding circuitry and enable generation circuitry. As a node receives address information, it decodes part of the address information and enables some of the nodes connected to it, passing the remainder of the address information to the enabled nodes. This process continues until an end node is reached which is connected to the circuit point which is to be monitored. Data generated at the monitored point is passed back though the enabled nodes to the external data port.
In accordance with one embodiment, the nodes are connected in a tree configuration, with each node belonging to one level of the tree.
In accordance with another embodiment, the end nodes are isolated from the circuit points to be monitored until the end nodes are enabled. In this manner an end node does not load the monitored circuit point when monitoring of that point is not taking place.
REFERENCES:
patent: 5793941 (1998-08-01), Pencis et al.
patent: 6324496 (2001-11-01), Alur et al.
patent: 10106262 (1998-04-01), None
Whetsel, Lee; “Hierarchically 1149.1 Applications in a System Environment”; Proceedings of the International Test Conference, US, New York, IEEE; 1993; Paper 23.1, pp. 517-526.
Kudirka & Jobse LLP
Sun Microsystems Inc.
Tu Christine T.
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