Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-09-13
2001-07-31
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060, C365S230080
Reexamination Certificate
active
06269028
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to data readout circuits, and more particularly to a multistage readout circuit and method for a semiconductor storage device, or the like.
BACKGROUND OF THE INVENTION
Typically, semiconductor storage devices have included memory cells that can store one of two states. Thus, a circuit for reading data (a readout circuit) may compare a memory cell data signal with a reference signal. If a memory cell data signal is greater than a reference signal, the memory cell is known to store one value (e.g., a “1”). If a memory cell data signal is less than a reference signal the memory cell is known to store another value (e.g., a “0”)
To achieve greater density, some semiconductor devices have included memory cells that may have more than two states. In some approaches data values may be read from a memory cell in a multistage fashion. In particular, a word line may be driven to different levels at different stages in the readout operation. At each word line level (stage) a data value may be read and latched. Latched data values may then be logically combined, by an encoder or the like, to generate an output signal.
To better understand multistage readout circuits, an example of a conventional multistage readout circuit will now be described with reference to
FIGS. 8 and 9
.
FIG. 8
is a circuit diagram of a conventional multistage readout circuit. The circuit of
FIG. 8
may read a data signal that may be at one of four levels. A multistage readout operation can encode the level into a two digit output value.
Referring now to
FIG. 8
, a conventional multistage readout circuit may include a readout circuit
011
that may be connected to a memory cell
012
, an encoder circuit
017
, and an output circuit
018
. A readout circuit
011
may include a sense amplifier
013
, a second stage latch circuit
141
, a first stage latch circuit
142
, and a third stage latch circuit
143
. An encoder circuit
017
can include clocked inverters
251
and
252
, as well as an inverter
241
and an exclusive OR (XOR) gate
015
.
FIG. 9
illustrates a truth table representing the response of the circuit of FIG.
8
.
FIG. 9
shows four possible memory cell states VT
0
to VT
3
. As but one of the many possible examples, such states (VT
0
to VT
3
) may represent memory cell threshold voltages, with VT
0
being a lowest threshold voltage and VT
3
being a highest threshold voltage.
As noted above, a four state memory cell value (VT
0
to VT
3
) may be encoded into a two digit binary value. In
FIG. 9
, the two digit binary value may include LOWER DATA value and an UPPER DATA value. Further, a particular state of a memory cell can be detected by driving a word line to a different level at three different stages. An output value may then be latched at each stage, with values of different stages being combined to generate output values.
FIG. 9
also shows one example of how a memory cell may respond at each stage. For example, if a memory cell had a state VT
0
, each stage (e.g., word line voltage level) would turn on the memory cell. Thus, the FIRST STAGE, SECOND STAGE and THIRD STAGE columns would all have the values “ON.”As another example, if a memory cell has a state VT
2
, the memory cell would remain off for the first and second stage word line voltages. However, for a third stage word line voltage, the memory cell would turn on. Thus, the FIRST STAGE, SECOND STAGE and THIRD STAGE columns would have the values “OFF,” “OFF” and “ON,” respectively.
Having described the general components and response of a conventional multistage readout circuit, the operation of the circuit will now be described in conjunction with FIG.
3
.
FIG. 3
is a timing diagram showing various signals that may be activated in a multistage readout operation. A WORD LINE LEVEL signal shows the various levels that a word line can be driven to in determining a memory cell state. A &phgr;
2
signal can activate a second stage latch circuit
141
, thereby inputting an output of a sense amplifier
013
into the second stage latch circuit
141
. Similarly, &phgr;
1
and &phgr;
3
signals can activate first and third stage latch circuits
142
and
143
, respectively, thereby inputting an output of a sense amplifier
013
into such latch circuit.
Two control signals, AL and BL are also shown. When control signals AL and BL are low and high, respectively, clocked inverter
252
can be active while clocked inverter
251
can be inactive. When control signals AL and BL are high and low, respectively, clocked inverter
251
can be inactive while clocked inverter
252
can be active. The alternate activation of clocked inverters
251
and
252
can provide LOWER DATA and UPPER DATA values to an output circuit
018
in a time multiplexed fashion.
FIG. 3
also includes various time periods, shown as T
1
to T
4
, and T
2
′. The operation of the conventional multistage readout circuit will now be described with reference to such time periods.
At a time period T
1
, a word line can be driven to a second (2) of three active levels. Thus, such a time period may be conceptualized as a second stage of a multistage readout. With a word line at a level
2
, a sense amplifier
013
can output a high or low level according to the particular state of a memory cell. In the response described, a level
2
word line value can result in a memory cell being ON if the memory cell has the VT
0
or VT
1
state, and being OFF if the memory cell has the VT
2
or VT
3
state. If a memory cell is ON, a sense amplifier
013
can output one value (e.g., high). Conversely, if a memory cell is OFF, a sense amplifier
013
can output another value (e.g., low).
Also during time period T
1
, a &phgr;
2
signal can transition low, enabling a sense amplifier output to be provided to a second stage latch circuit
141
. At the same general time, control signal AL can be high and control signal BL can be low, turning on clocked inverter
251
and turning off clocked inverter
252
. Thus, a value in second stage latch circuit
141
can be output to output circuit
018
while a previously encoded value output from inverter
241
can be isolated from output circuit
018
by way of clocked inverter
252
. It is noted that latch circuits (
141
,
142
or
143
) and/or output circuit
018
can invert or not invert a received input signal.
In this way, a LOWER DATA value can be provided to an output circuit
018
.
At a time period T
2
, a word line can be driven to an inactive level (
0
). In the response described, a level
0
word line value can result in a memory cell being OFF regardless of the memory cell state.
Also during time period T
2
, a &phgr;
2
signal can transition high, and second stage latch circuit
141
can latch the second stage result of the readout operation. Control signal AL can remain high and control signal BL can remain low.
At a time period T
3
, a word line can be driven to a first (
1
) of three active levels. Thus, such a time period may be conceptualized as a first stage of a multistage readout. With a word line at a level l, a sense amplifier
013
can output a high or low level according to the particular state of a memory cell. In the response described, a level
1
word line value can result in a memory cell being ON if the memory cell has the VT
0
state, and being OFF if the memory cell has the VT
1
, VT
2
or VT
3
state.
Also during time period T
3
, a &phgr;
1
signal can transition low, enabling a sense amplifier output to be provided to a first stage latch circuit
142
. At the same general time, control signal AL can be low and control signal BL can be high, turning off clocked inverter
251
and turning on clocked inverter
252
. Thus, a value in a second stage latch circuit
141
can be isolated from output circuit
018
while the output from inverter
241
can be provided to output circuit
018
.
At a time period T
4
, a word line can be driven to a third (
3
) of three active levels. Thus, such a time period may be conceptualized as a third stage of a multistage readout
Le Vu A.
NEC Corporation
Walker Darryl G.
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