Method and apparatus for monitoring yield of integrated...

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S010000

Reexamination Certificate

active

11411310

ABSTRACT:
A method for analyzing a structured integrated circuit is provided. The method includes identifying a random logic region of the structured integrated circuit. The structured integrated circuit includes a predefined layout for transistors and basic interconnections to define a set of logic elements. A tile array of basic logic cells is integrated throughout the identified random logic region. The tile array of basic logic cells is defined from the set of logic elements of the structured integrated circuit. The tile array of basic cells enables communication of testing signals along the tile array of basic logic cells in a first and a second direction. The first and second directions are different from one another. The testing signals help to identify one or more errors in the tile array of basic logic cells. The array format assists in diagnosing and curing defects in the tile array of basic logic cells. The errors are pinpointed to a basic logic cell at the intersection of the first and second direction.

REFERENCES:
patent: 5512397 (1996-04-01), Leedy
patent: 6222382 (2001-04-01), Jefferson et al.
patent: 2004/0010741 (2004-01-01), Forlenza et al.

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