Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With measuring – sensing – detection or process control means
Reexamination Certificate
1999-01-05
2003-10-14
Lund, Jeffrie R. (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
With measuring, sensing, detection or process control means
C156S345260, C156S345270, C156S345280
Reexamination Certificate
active
06632321
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor wafer processing systems, and more particularly, to method and apparatus for monitoring, processing and fabrication of such wafers using interferometric in situ measurement of the etch rate.
2. Description of Background
Integrated circuit wafer processing systems, particularly those which fabricate VLSI circuits on silicon wafers, can use many processes to form the circuit features on a wafer. One of the more prevalent processes is “dry etching” where a reactive gas in a plasma state is used to react with material on the wafer surface or an underlying substrate through a series of photoresist masks to produce the desired circuit features. Dry etching, also known as reactive ion etching (RIE), requires constant monitoring of the process to produce the desired results. Even relatively small uncontrolled changes in process parameters such the composition, pressure, flow rate or the ionization state of the etching gas, or the wafer temperature, electrode bias, etc. may cause unsatisfactory results.
When etching a three dimensional structure, conditions at the etch front change significantly during processing. The presence of sidewalls in the vicinity of the etching surface influences the influx of neutrals, ions and inhibitor precursors as well as the removal of reaction products causing changes in the etch rate. This effect is called aspect ratio dependent etch rate (ARDE) (also known as RIE lag), and as the name suggests the etch rate changes with the aspect ratio of a feature and not the etch depth. The aspect ratio of a feature is generally given by the ratio of the depth of the feature to the width of the feature.
The modality of ARDE is not fully understood and is a highly complex phenomenon. Various models have been proposed to explain the change in etch rate with increasing aspect ratio and differ mainly in which aspect of the etch mechanism, the ionic or the neutral component, is emphasized. Those studies which concentrate on the ionic component investigate such mechanisms as mask charging, ion shadowing, and localized surface charging giving rise to a significant ion flux to the sidewall. The ionic component etching may also be influenced by the power density loss at the bottom of the feature and the deposition of passivating layers at the bottom of the etched feature. This modality of etching is therefore very complex, hard to control and has some particularly detrimental effects to the etched feature including sidewall imperfections.
The influence of the neutral species on ARDE can be described by the easier to control effects of neutral shadowing and Knudsen transport. In a model proposed by Coburn and Winters in Applied Physics Letters 55 (1989) 2730, the neutral species effects on ARDE are described with the assumption that the etch rate is determined solely by the reaction of neutral etch species and the ionic component is neglected. Further, it is assumed that there is no etching of the sidewalls and the neutral species are reflected diffusely when colliding with the sidewall. Therefore, it would be highly desirable to control the ARDE of an integrated circuit etching process by the control of the neutral species effects of etching.
As feature size in modern integrated circuit fabrication continues to shrink, aspect ratios in general become larger and mask layers thinner. It is desirable to control the complex ARDE rate while fabricating an integrated circuit upon a semiconductor wafer.
Therefore, a need exists in the art for a method and apparatus for measuring and controlling the etch rate during the fabrication of integrated circuits that contain high aspect ratio features.
SUMMARY OF THE INVENTION
In one aspect of the invention, an apparatus for controlling a wafer processing system having a chamber and a pedestal within said chamber comprises an interferometer for generating a signal indicative of a rate of an aspect ratio dependent etch (ARDE) occurring within said chamber, and a controller coupled to said interferometer and said wafer processing system, for varying one or more process parameters of said wafer processing system in response to said signal, wherein the controller comprises an etch rate processing routine to control the rate of the aspect ratio dependent etch, the etch rate processing routine being capable of executing the steps of measuring an actual etch rate, determining a desired etch rate, comparing the actual etch rate to the desired etch rate, and varying one or more of the process parameters of the wafer processing system to change the actual aspect ratio dependent etch rate occurring in the chamber.
In another aspect of the invention, an apparatus for controlling a wafer processing system having a chamber comprising a pedestal to support a substrate for the etching of features on the substrate comprises an interferometer capable of generating a signal indicative of a rate of an aspect ratio dependent etch of the features being etched on the substrate, and a controller coupled to the interferometer and the wafer processing system, the controller being adapted to vary one or more process parameters of the wafer processing system in response to the signal, wherein the controller comprises an etch rate processing routine to control the rate of the aspect ratio dependent etch, the etch rate processing routine capable of executing the steps of measuring an actual etch rate, determining a desired etch rate, comparing the actual etch rate to said desired etch rate to determine an etch rate error, and varying one or more of the process parameters.
In another aspect, the invention provides a method and apparatus for monitoring, measuring and/or controlling the etch rate in a semiconductor wafer processing system. Specifically, a wafer professing system has a monitoring assembly which comprises an electromagnetic radiation source and detector which interferometrically measures the etch rate. The source, preferably a UV light source, is directed at a portion of the wafer surface where the etching is taking place. A portion of the UV light reflects back from the surface of the features of the wafer and another portion of the UV light reflects from the bottom of the features. There is a difference in phase between these two portions due to the extra distance of travel for the portion reflected from the bottom of the features. The difference in these phases forms an interference pattern which is more intense where the differently phased first and second portions of the light combine or interfere constructively and less intense where they cancel. The interference pattern is proportional or representative of the rate of change in the etch depth. The actual rate of change of the etch as it progresses is measured by this technique and is compared to a model of a desired rate of change in a controller. The error between the actual rate of change and the desired rate of change is then used to vary at least one of the process parameters of the system in a direction tending to null the difference. The actual rate of change is also an indicator of RIE lag (i.e., the change in etch rate that depends upon aspect ratios).
According to one aspect of the invention, the control of the parameters of the system is made to maintain the etch rate constant over the process. This will provide uniformity to the features particularly for a wafer with a high aspect ratio or with an ARDE feature.
According to another aspect of the invention, important process parameters such as etch gas flow, chamber pressure, source power and cathode temperature, either alone or in combination, can be used to control RIE lag.
These and other objects, aspects and features of the invention will be more clearly understood and better described when the following detailed description is read in conjunction with the attached drawings.
REFERENCES:
patent: 4208240 (1980-06-01), Latos
patent: 4367044 (1983-01-01), Booth, Jr. et al.
patent: 4953982 (1990-09-01), Ebbing et al.
patent: 5200
Grimbergen Michael
Lill Thorsten
Mui David
Applied Materials Inc
Bach Joseph
Janah Ashok K.
Lund Jeffrie R.
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