Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-17
2006-01-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C703S015000, C324S1540PB
Reexamination Certificate
active
06988229
ABSTRACT:
A system for monitoring and controlling boundary scan chains in real time that does not require the use of test vectors or test executives. The system automatically builds virtual Devices Under Test (DUT's) from user provided Boundary Scan Description Language (BSDL) files and displays them on the computer display. The virtual devices are connected to a port on the computer and the scan button is pressed to invoke a boundary scan. The results are displayed as color coded “pins” on a computer display to indicate if the pin is at a logic high, a logic low, or is toggling. Logic values may be forced on the pin via a point-and-click graphical user interface, again bypassing the need for test vectors. Graphical indicators and controls are provided by the system to help simplify monitoring and controlling of the boundary scan chain.
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Britt Cynthia
De'cady Albert
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