Method and apparatus for monitoring address translation performa

Details Method and apparatus for monitoring address translation performa Method and apparatus for monitoring address translation performa

1996-10-28

1999-08-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

39518401, 39518301, 39518501, 364550, 36455101, G06F 1200, G06F 1130

Patent

active

059374373

ABSTRACT:
Effective-to-real address translation performance in a processor is monitored by counting selected events significant to evaluation of effective-to-real address translation in the processor to identify effective-to-real address translation bottlenecks. At least one performance monitor counter, the operation of which is controlled by a monitor mode control register, is embedded in the processor to noninvasively perform such counting. Examples of the events counted may include translation lookaside buffer misses, page table walks, or page table walk duration, taken alone or in any combination. Events lasting longer than a predetermined threshold, such as stalls lasting longer than two processor cycles, may also be selectively counted.

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Hennessy & Patterson, "Computer Architecture A Quantitative Approach", 2nd Ed., pp. 384, 422-447, Jan. 1996.

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