Method and apparatus for memory self testing

Details Method and apparatus for memory self testing Method and apparatus for memory self testing

2007-09-11

2007-09-11

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000, C714S720000

Reexamination Certificate

active

10025816

ABSTRACT:
A self-test controller10is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller10.

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patent: 0 472 818 (1992-03-01), None

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