Method and apparatus for memory self testing

Details Method and apparatus for memory self testing Method and apparatus for memory self testing

2006-06-13

2006-06-13

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07062689

ABSTRACT:
A self-test controller for memory devices is provided with an integrated circuit. The self-test controller produces physical memory address values for driving desired memory tests. A mapping circuit serves to map these physical memory address signals to logical memory address signals as required by the particular memory devices. In this way a generic self-test controller may be provided that is able to drive tests within multiple different memory devices by providing a relatively simple mapping circuit.

REFERENCES:
patent: 6469945 (2002-10-01), Patti et al.
patent: 2003/0167428 (2003-09-01), Gold
Synopsys; “DesignWare Memory BIST MacroCell;” 2001.

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