Static information storage and retrieval – Read/write circuit – Testing
Patent
1993-12-08
1994-12-20
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Testing
371 101, 371 111, 371 212, G11C 1300
Patent
active
053750918
ABSTRACT:
A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
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Berry, Jr. Robert W.
Koenemann Bernd K. F.
Scarpero, Jr. William J.
Shephard, III Philip G.
Wagner Kenneth D.
Augspurger Lynn L.
Fears Terrell W.
International Business Machines - Corporation
Visserman Peter
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