Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-09-27
2004-08-31
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000
Reexamination Certificate
active
06785793
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to memory controllers, and more particularly to a method and apparatus for reducing memory access latencies and improving bandwidth.
2. Description of the Related Art
Modem memory, such as dynamic random access memory (DRAM), is used throughout the computer industry. Memory is organized into pages. Each page of memory contains data for a number of contiguous memory locations. Memory devices, such as DRAM, are further organized into a small number of banks per DRAM device (e.g., four banks). Each of these devices have many pages per bank. Only a single page can be accessed from a bank at a time. Before a particular page within a bank can be accessed, that page must be opened using an “activate” command. This activate command is also known as a “row” command. A memory request requiring a page to be opened is called a page-empty access request. A memory request to a page that has already been opened is known as a page-hit access request. A page may be closed using a pre-charge command.
If page P
0
is open when a request is received to access a location in page P
1
that happens to be located in the same memory bank as P
0
, page P
0
must first be closed before page P
1
can be opened. A page conflict, such as this, occurs when one page must be closed before a desired page can be opened. This situation is known as a page-miss access.
Memory access latency is much greater for page misses than for page hits. Page hit and page empty accesses to different memory banks may be interleaved such that available data bandwidth may be maintained. Page miss accesses, however, typically result in a reduction of available data bandwidth. Therefore, page misses are particularly detrimental for DRAM performance.
Synchronous DRAM double data rate (SDRAM/DDR) memory technology has a small number of DRAM banks. SDRAM/DDR memory is a type of SDRAM that supports data transfers on both edges of each clock cycle, effectively doubling the memory chip's data throughput. Due to SDRAM/DDR memory containing a small number of memory banks can lead to performance bottlenecks because of page miss and page empty accesses. This performance bottleneck can lead to increased memory latency and lower bandwidth, thus, lower platform performance. In memory controllers there is a dilemma in whether to keep pages open until a page conflict occurs at which point the page is closed, or pages can be closed aggressively. Neither of these techniques, however, is optimal for all workloads.
SDRAM/DDR memory provides a mechanism called auto-pre-charge, which can be used to automatically pre-charge (close) a memory bank as soon as a memory request is completed. This can be useful in developing a page-closing policy that is more suited for SDRAM/DDR memory devices. An advantage that can be seen by having an automatic pre-charge policy, as compared to a policy that issues an explicit pre-charge command, is that it obviates the need for an explicit pre-charge command. This can reduce the DRAM command bus available bandwidth. Therefore, freeing up command bus slots for other commands. An auto-pre-charge policy, however, not only converts all page-miss accesses to page-empty accesses (i.e., reducing latency), but the auto-pre-charge policy also does the same for all page-hit accesses. Therefore, resulting in longer latency for accesses that would have just reused a page already opened for an earlier request. Depending on the amount of locality present in the access stream, a substantial loss of performance can result.
Existing DRAM technology typically issue a series of DRAM commands to DRAM devices connected in the system. These DRAM commands cause the DRAM device to perform various functions, such as close a previously opened page (pre-charge), open a new page (activate) and read data from or write data to a DRAM device. For electrical reasons, a certain amount of time must be allowed to pass between successive commands to a same DRAM memory bank. This allotted time is specified in the manufacturers' specifications and is known as DRAM timing constraints.
FIG. 1
illustrates examples of commands issued to read data from memory, as well as associated timing constraints. DRAM commands stream
100
illustrates reading from an idle DRAM bank (page empty). DRAM command stream
105
illustrates reading from a DRAM bank with another page open (page miss). As illustrated in DRAM command streams
100
and
105
, when DRAM commands for successive memory accesses are issued sequentially, the DRAM subsystem will remain idle during the times allocated for time constraints. If these idle DRAM command bus slots are not otherwise used, this can lead to reduced memory system efficiency and lower performance.
REFERENCES:
patent: 6154826 (2000-11-01), Wulf et al.
patent: 6173345 (2001-01-01), Stevens
patent: 6418525 (2002-07-01), Charney et al.
patent: 6510497 (2003-01-01), Strongin et al.
patent: 6546439 (2003-04-01), Strongin et al.
patent: 2002/0065981 (2002-05-01), Jenne et al.
patent: 0473302 (1992-03-01), None
patent: 0940757 (1999-09-01), None
patent: WO01/16715 (2001-03-01), None
Notification of Transmittal of International Search Report, International Application No. PCT/US 02/31161, Nov. 10, 2003.
Aboulenein Nagi
Crocker Ken M.
Huggahalli Ram
Madavarapu Vamsee K.
Osborne Randy B.
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