Method and apparatus for measuring duty cycle distortion on...

Details Method and apparatus for measuring duty cycle distortion on... Method and apparatus for measuring duty cycle distortion on...

2007-12-11

2007-12-11

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C327S175000, C327S265000

Reexamination Certificate

active

11201462

ABSTRACT:
A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to sample the logic value of a test signal after the test signal has traversed a path under test (PUT). A counter is used to determine the number of logic high valued samples and the number of logic low valued samples during a test period. A ratio is then taken to determine the resulting duty cycle for the test period.

REFERENCES:
patent: 6219305 (2001-04-01), Patrie et al.
U.S. Appl. No. 11/061,697, filed Feb. 18, 2005, Verma et al.
U.S. Appl. No. 10/255,502, filed Sep. 26, 2003, Lesea.
U.S. Appl. No. 10/402,837, filed Mar. 27, 2003, Lesea.
U.S. Appl. No. 11/201,688, filed Aug. 11, 2005, Verma.

Affiliated with

Also associated with

Rating

Method and apparatus for measuring duty cycle distortion on... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for measuring duty cycle distortion on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for measuring duty cycle distortion on... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3872209