Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-02-03
1999-07-13
Pan, Daniel H.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711142, 711143, 711145, 39580041, G06F 940, G06F 1204
Patent
active
059241209
ABSTRACT:
Use of an internal processor data bus is maximized in a system where external transactions may occur at a rate which is fractionally slower than the rate of the internal transactions. The technique inserts a selectable delay element in the signal path during an external operation such as a cache fill operation. The one cycle delay provides a time slot in which an internal operation, such as a load from an internal cache, may be performed. This technique therefore permits full use of the time slots on the internal data bus. It can, for, example, allow load operations to begin at a much earlier time than would otherwise be possible in architectures where fill operations can consume multiple bus time slots.
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Keller James
Meyer Derrick R.
Razdan Rahul
Webb, Jr. David Arthur James
Digital Equipment Corporation
Pan Daniel H.
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