Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-09-26
2006-09-26
Kerveros, James C. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000
Reexamination Certificate
active
07114111
ABSTRACT:
A method and an apparatus for determining functional coverage of a design for a device under test (DUT), the design being encapsulated in a DUT circuit design specification, in a test environment during a design test verification process.The method and apparatus utilize a coverage metric constructed from a plurality of coverage items. A first step involves obtaining a coverage group from the DUT design, for examining during the design test verification process. The coverage group includes at least one functional coverage item. Then, a set of input values is provided to the design test verification process. Next, design test verification process is performed with the set of input test values to obtain a value for each coverage item.Next step involves examining obtained coverage by comparing the value obtained from each coverage item with a coverage goal. Finally, the set of input test value is automatically altered in accordance with the examination of the obtained coverage.
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Cadence Design (Isreal) II Ltd.
Kerveros James C.
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