Method and apparatus for mapping design memories to...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

07424687

ABSTRACT:
A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.

REFERENCES:
patent: 6738953 (2004-05-01), Sabharwal et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for mapping design memories to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for mapping design memories to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for mapping design memories to... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3971949

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.