Method and apparatus for mapping design memories to...

Details Method and apparatus for mapping design memories to... Method and apparatus for mapping design memories to...

2008-09-09

2008-09-09

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11280110

ABSTRACT:
A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.

REFERENCES:
patent: 6738953 (2004-05-01), Sabharwal et al.

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