Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
1999-02-26
2002-06-04
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S056000, C710S005000, C712S024000, C712S213000, C712S210000, C712S240000, C712S201000, C712S300000
Reexamination Certificate
active
06401144
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of memory contained within Central Processing Unit (CPU) architecture. More particularly, the present invention describes a method and apparatus which ensures that transfers of data from different CPU memory locations to a peripheral device are completed prior to the peripheral device operating on the transferred data.
2. The Background Art
The total memory space available within which a CPU may read or write is typically assigned to a number of external and internal devices of different types. The characteristics of a given device determine how the processor interfaces with that device and the memory space associated with that device. Failure to follow the rules associated with a particular device and the associated memory space, often results in improper operation.
For example, within CPU's found in many computers today such as a Pentium Pro, there exists a set of registers that platform-specific software, e.g. Basic Input-Output System, Hardware Abstraction Layer, etc. sets up to define the rules within which segments of memory will be operated.
Designated the Memory Type and Range Registers (MTRR), these registers are set up during a boot cycle to define the various regions of memory available, and how the processor core instruction set and memory caches should behave when accessing each region for a read or write operation.
In computers having a Pentium Pro CPU, memory regions may be defined at startup as one of five types, namely Uncacheable memory (UC), Write Combining (WC) memory, Write Through (WT) memory, Write Protect (WP) memory, and Write Back (WB) memory.
Data written into WC memory is stored as it arrives, in lines of 32-bytes each. However, when the time comes for transmitting the data out of cache memory to the peripheral device, the data may leave the WC memory in a different order. The arrival of a second set of data at the peripheral device prior to a first set of data arriving may trigger operations within the peripheral device to begin prior to receipt of necessary data within the first set of data being received. Unintended results often follow, including the possibility of a failed operation.
It would therefore be beneficial to provide a method and apparatus for ensuring that all required data has been received by a peripheral device prior to performing operations requiring that data.
SUMMARY OF THE INVENTION
A method and apparatus for ensuring that information transfers from memory to a peripheral device are complete prior to the peripheral device executing instructions responsive to the content of the information is described. The method includes identifying lines of data to be written, determining a unique start code to be used for that data, and embedding that start code into that data. When the proper number of lines of data have arrived in peripheral device memory, the pending operation is executed.
REFERENCES:
patent: 4292667 (1981-09-01), Catiller et al.
patent: 4843544 (1989-06-01), DuLac et al.
patent: 4849747 (1989-07-01), Ogawa et al.
patent: 4864495 (1989-09-01), Inaba
patent: 4875196 (1989-10-01), Spaderna et al.
patent: 5664135 (1997-09-01), Schlansker et al.
patent: 5867699 (1999-02-01), Kuslak et al.
patent: 5881260 (1999-03-01), Raje et al.
patent: 6275927 (2001-08-01), Roberts
Intel Corporation
Lee Thomas
Peyton Tammara
Ritchie David B.
Thelen Reid & Priest LLP
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