Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-12
2004-01-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06675362
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the development and debug of circuit tests, and particularly, to the development and debug of in-circuit tests which are designed to test the functionality of analog components mounted on a printed circuit board.
BACKGROUND OF THE INVENTION
The development of circuit tests for the purpose of in-circuit testing is a costly and time consuming process. Not only must tests be written (or generated), but thereafter the tests must be debugged.
Circuit tests are typically debugged on a reactive basis. That is, tests are repeatedly executed with respect to one or more circuit boards while waiting for a component to be designated FAILED. When a component is designated FAILED, it must then be determined whether the component has truly failed, or whether execution of a test with respect to the component has led to the generation of a “false fail”. A “false fail” is defined herein as a fail which is triggered as a result of a test misadjustment rather than an actual component failure.
If it is determined that the execution of a test with respect to a particular component has led to the generation of a false fail, the test must be debugged so as to prevent a reoccurrence of the false fail. Such a debug effort is a “reactive” debug effort. That is, an in-circuit test (ICT) programmer must 1) wait for a component to be designated FAILED, 2) determine whether the fail is a false fail, and then 3) debug a circuit test if the test is believed to have caused the false fail.
SUMMARY OF THE INVENTION
A problem which is encountered when debugging circuit tests is that tests are not manageable other than on an individual basis. That is, a circuit test is individually developed and maintained for each component in a circuit. As a result, many debug efforts are unnecessarily repeated.
For example, consider a circuit comprising twenty 10 k&OHgr; resistors. Presently, each of these resistors has to be associated with its own unique circuit test, and a debug of the circuit tests associated with the twenty resistors results in twenty different debug efforts. Since the twenty resistors are subject to manufacturing variances, slight variations in the twenty resistors will likely lead to the twenty resistors generating false fails at different times. If an ICT programmer is lucky, “gross” test misadjustments will result in many of the resistors being falsely designated as FAILED at about the same time, and the programmer can make similar test adjustments to the tests associated with all of the resistors. However, in later stages of a debug effort, the resistors are likely to be falsely designated as FAILED at widely varying times, and the programmer will have to adjust the tests associated with each of the resistors in a distinct and remote debug effort. Since there are many test solutions which a programmer can try, he or she is likely to make different adjustments with respect to each of the different resistor tests. It is also quite probable that different programmers will be responsible for making the different test adjustments as the different tests produce false fails.
The inventors propose methods and apparatus for grouping circuit tests to make them more manageable. One advantage of the increased manageability is that duplicate debug efforts such as those discussed in the preceding paragraph can be avoided.
The techniques disclosed herein help to manage circuit tests by first forming component groups, and then establishing for each group a circuit test which is common to the components of the group. When one component of a group is falsely designated as FAILED, the circuit test which is associated with the falsely failed component is debugged, and the debugged circuit test is then used as a template to update the circuit tests associated with other components in the falsely failed component's group. In this manner, circuit tests which are associated with non-failing components are debugged proactively. Proactive debugging not only reduces debug time, but also insures that circuit tests for like components retain a degree of uniformity.
In one embodiment of the invention, a test history log is maintained. The maintenance of a test history log is especially advantageous in that such a log can be used to not only track the test history of a particular component, but to track the test history of all of the components in a particular component group. Thus, if a test solution has already been tried and discarded with respect to one component in the group, an ICT programmer can avoid retrying the faulty test solution with respect to other components in the same group.
With existing techniques for developing and debugging circuit tests, there are no economies of scale. Thus, the time required to develop and debug circuit tests for a particular circuit is more or less a function of the number of components in the circuit. Consider, for example, the following two circuits:
Circuit A = 1,000 components
= 2 days for development and initial debug of tests
(gross debug)
= 4 weeks for stabilization of tests (fine debug)
Circuit B = 250 components
= ½ day for development and initial debug of tests
(gross debug)
= 1 week for stabilization of tests (fine debug)
Since Circuit B has 75% fewer components than Circuit A, the time required to develop and debug circuit tests for Circuit B is 75% less than the time required to develop and debug circuit tests for Circuit A.
With the techniques disclosed herein, the time required to develop and debug circuit tests is not related to the number of components in a circuit, but rather the number of component groups in a circuit. Component groups may be formed by identifying various electrical characteristics of a number of components which exist in a circuit, and then grouping the components in response to their electrical characteristics. Electrical characteristics may comprise characteristics such as component type, component value, and circuit topology (i.e., the way in which a component is topologically connected within a circuit).
By proactively debugging circuit tests, and avoiding repetition of faulty test solutions, an ICT programmer can achieve stabilization of all of the tests in a test suite much quicker than he or she could achieve same in the past. For example, refer back to Circuits A and B, supra. Although Circuit A has 1,000 components, it might only comprise
100
component groups. If so, the use of the proactive debugging techniques disclosed herein would reduce the time it takes to debug Circuit A to approximately one-tenth of the time it takes to debug Circuit A using current reactive debugging techniques.
The above embodiments of the invention assume that one has access to a mathematical circuit model or the like, from which electrical components and their characteristics may be identified for the purpose of grouping the components. In some cases, this information may not be available. For example, it is possible that one may only have access to an already generated test suite. In this case, electrical components may be grouped based on the test parameters which are found in already existing circuit tests. If the test parameters for two components are identical, then it typically follows that the two components are of the same type, value, and so on. If a test suite is largely generated from test libraries, and is generated in an automated way, then the grouping of a circuit's components by relying on test parameters found in the tests which are associated with the components should yield the same component groups as would be formed when grouping is based directly on the electrical characteristics of a number of components.
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Huetter John P.
Ortiz Richard D.
Sill Gale A.
Vu Duong Xuan
Agilent Technologie,s Inc.
Dimyan Magid Y
Smith Matthew
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