Method and apparatus for making mosfet's with elevated...

Details Method and apparatus for making mosfet's with elevated... Method and apparatus for making mosfet's with elevated...

1999-06-15

2001-02-13

Monin, Jr., Donald L. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S356000, C438S592000, C438S563000, C438S663000

Reexamination Certificate

active

06187642

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to MOSFET devices. Even more particularly, the present invention relates to MOSFET devices with raised (or elevated) source/drain extensions.
BACKGROUND OF THE INVENTION
In the prior art, MOSFETS with raised source/drain regions use source/drain extensions to connect a channel with the raised source/drain regions.
FIG. 1
is a schematic view of a prior art MOSFET
10
with raised source/drain regions
11
. The raised source/drain regions
11
are built on top of a substrate
12
surface. A gate oxide
14
is placed on the surface of the substrate
12
between the raised source/drain regions
11
. A gate
15
is placed over the gate oxide
14
. Side spacers
16
are placed adjacent to the gate
15
and gate oxide
14
and on the substrate
12
, separating the gate
15
and gate oxide
14
from the source/drain regions
11
. Source/drain extensions
17
are formed at and below the surface of the substrate
12
extending under the source/drain regions
11
, the side spacers
16
, and partly under the gate oxide
14
and the gate
15
. Isolation trenches
19
are cut into the surface of the substrate
12
around the source/drain extensions
17
to isolate the MOSFET
10
. The source/drain extensions
17
may be created through various processes with various doping concentrations. Throughout the specification and claims the phrase “source/drain extensions” will also include source/drain extension type structures created through various means such as lightly-doped-drain implants.
Deep source/drain junctions increase short-channel effects. An increased short-channel effect causes an increased off stage leakage current.
Elevated or raised source/drain MOS transistors have been developed to achieve shallow junctions while maintaining low sheet resistivity in the source/drain regions, as well as low silicided contact resistance without significantly increasing the junction leakage. Such raised source/drains are discussed in “Elevated Source/Drain MOSFET”, by S. S. Wong, et al. in IEDM Tech. Digest, December 1984, p. 634, and in “Raised Source/Drain MOSFET With Dual Sidewall Spacers” by Mark Rodder and D. Yeakley, IEEE Electron Device Letters, Vol. 12(3), March 1991, p. 89, and in “Low Resistance Ti or Co Salicided Raised Source/Drain Transistors For Sub-0.13 &mgr;m CMOS Technologies” by C. P. Chao, et al., IEDM Tech. Digest., December 1997. Source/drain junctions have been elevated, however, only in the heavily doped regions. In other words, the junction depths of source/drain extensions have not been reduced.
BRIEF SUMMARY OF THE INVENTION
It is an object of the invention to provide method and apparatus for reducing short channel effects.
It is another object of the invention to provide a MOSFET with shallower source/drain extensions.
It is another object of the invention to provide raised source/drain extensions.
Accordingly, the foregoing objects are accomplished by creating a MOSFET with partially raised source/drain extensions.
Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”


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patent: 5200352 (1993-04-01), Pfiester
patent: 5319232 (1994-06-01), Pfiester
patent: 5496750 (1996-03-01), Moslehi
patent: 5504031 (1996-04-01), Hsu et al.
patent: 5539229 (1996-07-01), Noble, Jr. et al.
patent: 5600165 (1997-02-01), Tsukamoto et al.
patent: 5693974 (1997-12-01), Hsu et al.
Wong S.S., D.R. Bradbury, D.C. Chen & K.Y. Chiu: “Elevated Source/Drain MOSFET”: IDEM 1984, pp. 634-635.
Mark Rodder and D. Yeakley: “Raised Source/Drain MOSFET with Dual Sidewall Spacers”: IEEE Electron Device Letters, vol. 12, Mar. 1991, pp. 89-91.
C.-P. Chao, K.E. Violette, S. Unnikrishnan, M. Nandakumar, R.L. Wise, J.A. Kittl, Q.-Z. Hong, and I.-C. Chen: “Low Resistance Ti or Co Salicided Raised Source/Drain Transistors for Sub-0.13 &mgr;m CMOS Technologies”: IEDM Technology Digest, Dec. 1997.

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