Method and apparatus for maintaining cache coherency in an integ

Electrical computers and digital processing systems: support – Computer power control – Power conservation

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711141, G06F 110

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active

060147512

ABSTRACT:
A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

REFERENCES:
patent: 5481731 (1993-03-01), Conary et al.
patent: 5530932 (1996-06-01), Carmean et al.
patent: 5632037 (1997-05-01), Maher et al.
patent: 5677849 (1997-10-01), Smith
patent: 5737746 (1998-04-01), Hardin et al.

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