MOS type integrated circuit having charging and discharging tran

Details MOS type integrated circuit having charging and discharging tran MOS type integrated circuit having charging and discharging tran

1985-12-05

1988-01-26

Wojciechowicz, Edward J.

357 234, 357 238, 357 239, 357 46, 357 90, H01L 2978

Patent

active

047219904

ABSTRACT:
A MOS integrated circuit includes one charging transistor and one discharging transistor. One end of the current path of the charging transistor is connected to one end of the current path of the discharging transistor. A high power voltage is applied to the other end of the current path of the charging transistor. The charging transistor charges the one end thereof to a predetermined voltage level. A low power voltage is applied to the other end of the current path of the discharging transistor. The discharging transistor discharges one end thereof to a predetermined voltage level. Each transistor includes layers of a low impurity concentration for weakening the surface electric field of the transistor, thereby reducing generation of hot electrons or impact ionization current. More hot electrons are generated in the charging transistor than in the discharging transistor. The weakening layers of the discharging transistor has, therefore, an impurity concentration higher than the weakening layers of the charging transistor.

REFERENCES:
patent: 4433257 (1984-02-01), Kinoshita
patent: 4521448 (1985-06-01), Sasaki
patent: 4599576 (1986-07-01), Yoshida et al.
Ogura, et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," IEEE Transactions on Electron Devices, vol. ED-27, No. 8, pp. 1359-1367, Aug. 1980.
IEEE Transactions on Electron Devices, vol. ED-29, 4/82, pp. 590-596.
IEEE Transactions on Electron Devices, vol. ED-30, No. 6, Jun. 1983, pp. 652-657.

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