Method and apparatus for low power memory bit line precharge

Details Method and apparatus for low power memory bit line precharge Method and apparatus for low power memory bit line precharge

2001-05-31

2003-09-30

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C365S185250, C365S230030, C365S230010

Reexamination Certificate

active

06629194

ABSTRACT:

BACKGROUND
1. Field
An embodiment of the present invention relates to the field of memory read accesses and, more particularly, to a low power memory bit line precharge scheme.
2. Discussion of Related Art
The increasing power consumption of microprocessors and other integrated circuits (ICs) has become one of the major issues for current and next generation designs. Power-related costs (e.g. cooling and power delivery) can have a significant impact on the overall cost of an integrated circuit chip and, therefore, cut into profit margins in an increasingly competitive marketplace. Additionally, high power consumption and junction temperatures can limit the performance of high-end microprocessors and other ICs.
More particularly, register files and other memory can consume a significant percentage of power on a microprocessor, for example. For current and next generation microprocessors, the size and number of register files and/or memory structures on a microprocessor continues to increase such that the percentage of overall power dissipation attributable to these structures is also expected to rise.


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