4. Static information storage and retrieval
  5. Plural shift register memory devices

Jiann-Cherng Lan

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Low power precharge scheme for memory bit lines

Static information storage and retrieval – Read/write circuit – Precharge
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Method and apparatus for low power memory bit line precharge

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate

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Multi-entry register cell

Static information storage and retrieval – Plural shift register memory devices
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Single stage pulsed domino circuit for driving cascaded...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2616766

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