Method and apparatus for low power data transmission

Details Method and apparatus for low power data transmission Method and apparatus for low power data transmission

1996-12-30

1998-11-03

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 98, 326121, 327403, 327404, H03K 190948, H03K 19096

Patent

active

058314539

ABSTRACT:
A method and apparatus for low power transmission of digital data. A low power data transmission circuit includes a pass gate having parallel-connected n and p-channel CMOS transistors that transmit input data. To reduce power in a first embodiment, a circuit disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle. In a second embodiment, the circuit disables the parallel-connected n-channel pass gate transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle. These low power data transmission circuits achieve substantial power savings by avoiding unnecessary charging and discharging of the pass gate transistors' gate capacitance on every clock cycle.

REFERENCES:
patent: 4571504 (1986-02-01), Iwamoto et al.
patent: 4577124 (1986-03-01), Koike
patent: 4611135 (1986-09-01), Nakayama et al.
patent: 5450019 (1995-09-01), McClure et al.

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