Method and apparatus for interfacing a processor with a bus

Details Method and apparatus for interfacing a processor with a bus Method and apparatus for interfacing a processor with a bus

1999-08-18

2002-08-06

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000, C711S100000, C711S111000, C711S150000

Reexamination Certificate

active

06430646

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to computer system architectures and more particularly to a processor interface.
BACKGROUND OF THE INVENTION
In a computer system (e.g., personal computer, laptop, personal digital assistant, etc.), the central processing unit (CPU) interfaces with a bus to communicate with other components in the computing system (e.g., north bridge). To support the interfacing, the CPU includes a plurality of cache line buffers (CLB), which provide the coupling to the bus. Typically, the CPU will include at least one CLB for fill operations (i.e., retrieving data from memory and storing it in cache) and at least one other CLB for flush operations (i.e., sending data from a cache to memory). In many systems, the CPU will contain a separate CLB for instruction cache fills, data cache fills, instruction cache flushes, and data cache flushes. While separate CLBs provide an easy implementation of an interface, it requires a substantial amount of circuitry, which increases die size.
In computing systems that include multiple CPUs, one bus interface implementation employs a separate integrated circuit to process bus arbitration and to provide the bus interfacing. As such the CPUs do not have direct access to the bus, which adds delays in the processing of data. In addition, the extra integrated circuit adds to the costs of the multiple CPU system, rendering it too costly for some applications.
Another multiple CPU computing system implementation has each CPU directly coupled to the bus, but each CPU is required to track the transactions of all of the CPUs. As such, each CPU is dependent upon the other CPUs to interface with the bus. For example, if the bus is capable for supporting eight concurrent transactions and the system includes three CPUs, each CPU will need to include a CLB capable of storing eight transactions. Each CLB stores the same data, thus limiting each CPUs number of transactions that may be queued in its CLB and creates a dependency between the CPUs.
Therefore, a need exists for a CPU interface that utilizes a single CLB for both cache and instruction transactions, and, in multiple CPU systems, allows the CPU to interface with the bus independently and to increase the number of transactions that it may queue with minimal additional CLB space.


REFERENCES:
patent: 6061765 (2000-05-01), Van Doren et al.
patent: 6101581 (2000-08-01), Doren et al.
patent: 6105108 (2000-08-01), Steely, Jr. et al.
patent: 6205506 (2001-03-01), Richardson

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