Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1998-07-08
2001-11-27
Smith, Matthew (Department: 2768)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S245000, C710S002000, C710S035000, C710S109000, C326S037000
Reexamination Certificate
active
06324642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to data transmission between a computer and a peripheral device. More particularly, the present invention pertains to a method for high-speed, bi-directional data communication across a parallel port.
2. Related Art
In the architectures of many personal computers (PCS), a parallel port is provided which allows communication between the personal computer and a peripheral device such as a printer. Communication between the PC and the peripheral device can be done either through a software handshaking protocol or through a hardware handshaking protocol. In a software handshaking protocol, the exchange of data is typically done with the exchange of command, data, and acknowledge messages. For example, for a PC to send a byte of data to a peripheral device may require the following steps:
1. PC checks control signal (or handshake) line to make sure peripheral device is ready for data.
2. PC places data onto data signal lines of the parallel port.
3. PC sets a signal on a control signal line to indicate that the data is on the parallel port.
4. Peripheral device reads data from data signal lines.
5. Peripheral device sets a signal on a control signal line to acknowledge receipt of data.
6. PC reads the acknowledge signal.
7. PC resets signal on the control signal line from step 3, above.
8. Peripheral device resets signal on the control signal line from step 5, above.
Steps 1 through 8 are then repeated for each byte transferred over the parallel port using this protocol.
A hardware handshaking protocol provides the use of control signal lines in conjunction with data signal lines to help streamline the transfer of data over the parallel port. Such a feature became available in 1994 and is presented, for example, as the Extended Capabilities Port (ECP) and Enhanced Parallel Port (EPP) modes of the IEEE (Institute of Electrical and Electronics Engineers, Inc.) std. 1284-1994 (see “IEEE Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers” (IEEE std. 1284-1994, Dec. 2, 1994)). Although virtually all PCS shipped today have built-in support for these hardware handshaking protocols, most are delivered with the capability turned off in the Basic Input/Output System (BIOS) code. Unless the user is sophisticated enough to reconfigure the BIOS code to enable the hardware handshaking protocol, this feature is typically not used. Also, although virtually all PCS are capable of reversing direction of the data lines on the parallel port (i.e., from the peripheral device back to the PC), this capability is typically turned off in the BIOS as well. In those systems, data transfers from the peripheral device to the PC must be communicated over five control signal lines in the parallel port that are always driven from the peripheral device.
Furthermore, a drawback of the software protocols described in the IEEE standard identified above is the amount of time (measured in Input/Output (I/O) transactions) it takes to send a byte of data over the parallel port. Even in a very high speed computer system using a Pentium® processor (Intel Corporation, Santa Clara, California) and a Peripheral Component Interconnect (PCI) bus (Rev. 2.1, PCI Special Interest Group, Hillsboro, Oreg., 1995), I/O transactions are typically conducted with the parallel port every microsecond, at best. Using the protocols described in this IEEE standard, may require the eight I/O transactions described above to send one byte of data over the parallel port. This leads to a maximum transfer rate of approximately 250 Kilobytes per second (KBps), and a typical value between 40 KBps and 100 KBps.
Accordingly, there is a need for a method to improve the data transfer rate over a parallel port for a PC or the like.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a system is provided for communicating data over a parallel port comprising. The system includes a host device and a parallel port coupled to the host device and adapted to be coupled to a peripheral device. The parallel port includes at least one data signal line and a first control signal line. The host device is adapted to place data on the data signal line of the parallel port and to toggle a signal on the first control signal line of the parallel port indicating that the data is ready to be read by the peripheral device.
REFERENCES:
patent: 4667286 (1987-05-01), Young et al.
patent: 5588114 (1996-12-01), Bhatin
patent: 5655135 (1997-08-01), Sholander et al.
patent: 5754881 (1998-05-01), Aas
patent: 5758188 (1998-05-01), Applebaum et al.
patent: 5867718 (1999-02-01), Intrater et al.
Martin Phil
Peek Greg
Yaple Nelson
Intel Corporation
Kenyon & Kenyon
Smith Matthew
Speight Jibreel
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