Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-07-30
2001-03-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06207512
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor devices and the fabrication thereof and, more particularly, to isolation and well regions formed in a substrate and the fabrication thereof.
BACKGROUND OF THE INVENTION
In one method of the related art P and N-channel MOS transistors are fabricated in a semiconductor substrate in a dual polysilicon gate process. In a dual polysilicon gate process, N-channel and P-channel gates are defined with separate individual masks, in contrast to a single polysilicon gate process wherein both the N-channel and the P-channel gates are formed using a single photolithographic process. The semiconductor substrate is doped with negative impurity atoms and positive impurity atoms to create negative and positive active regions respectively. These active regions can be thought of as having opposite polarities or opposite conductivities. One of the regions is created in the substrate while the other region is created in a well. The well is formed by doping a portion of the substrate to have a conductivity opposite to that of the original substrate.
FIGS. 1-3
show a cross sectional portion of a semiconductor wafer following process fabrication steps used in a method of the related art to form P- and N-channel MOS transistors. In
FIGS. 1-3
an N-well
5
has been created in a P-substrate
10
by conventional fabrication means.
The N-well is a counterpart to the P-substrate in that it functions as a region in which to form P-channel MOS transistors, while the P-substrate functions as a region in which to form N-channel MOS transistors. A P-type region and an N-type region are opposite of each other with respect to energy bands. An N-type region has many electrons in its conduction band, while a P-type region has relatively few electrons in its conduction band; and a P-type region has many holes in its valence band while an N-type region has relatively few holes in its valence band. Micro Chip, A Practical Guide to Semiconductor Processing, by Peter Van Zant and Electronic Principles, third edition, by Albert Paul Malvino are herein incorporated by reference in order to determine a minimal knowledge of someone skilled in the art.
Thick oxide
25
is grown to form field oxide regions to electrically isolate active regions from each other, and a thin gate oxide
30
is grown overlying the active regions. The formation of the thick oxide layer
25
and the gate oxide layer
30
are well known to those skilled in the art.
Referring to
FIG. 1
, the conventional fabrication means is continued, and a polysilicon layer
31
is masked with photoresist to define an N-channel gate polysilicon and interconnect and an N-well tie. The polysilicon is etched and spacers
33
are formed on opposing sides of the polysilicon remaining after the etch.
The in-process wafer is bombarded with negative ions to form N-type regions in the active regions not covered with polysilicon
31
. N-type active regions
35
function as source/drain regions of an N-channel MOS transistor, and polysilicon layer
31
interposed between the regions
35
functions as the gate of the N-channel MOS transistor thus formed. N-type active region
45
is an N-well tie. An N-well tie is a region formed in the surface of the substrate in the N-well region that provides ohmic contact of the N-well to an external supply potential.
In
FIG. 2
a second photoresist mask
50
defines P-channel gate polysilicon and interconnect and protects the N-channel gate polysilicon and N-type active regions
35
and
45
previously defined.
In
FIG. 3
the polysilicon layer
31
remaining exposed at this juncture are etched. The substrate is now bombarded with positive ions and P-type active regions
60
and
65
are formed in the surface of the substrate. It is important to note that the thick oxide regions
25
also function as masks during both the positive and negative ion bombardments that form the N-channel and P-channel source/drain regions and well/substrate ties.
P-type active regions
60
function as the sources/drain regions of a P-channel MOS transistor. Polysilicon layer
31
interposed between source/drain regions
60
functions as the gate of the P-channel MOS transistor thus formed. P-type active region
65
is a P-substrate tie and provides ohmic contact to the substrate from an external supply potential.
Although it would seem that the N-well tie
45
shown in the cross section comprises two portions, the N-well tie
45
may actually be a continuous ring surrounding the P-channel transistors, and the P-substrate tie
65
may actually be a continuous ring surrounding the N-well
5
. In further fabrication steps, contacts (not shown) are formed with the P-substrate tie
65
and the N-well tie
45
as well as the source/drain and gate terminals of the MOS devices. The P-substrate tie
65
is connected to a potential having a low voltage, typically ground, and the N-well tie
45
is connected to a potential having a high voltage, typically V
CC
. The P-substrate tie and N-well tie help prevent latch up of the device when interposed between the N-MOS and P-MOS device.
Latchup occurs when two parasitic cross coupled bipolar transistors are actuated and essentially short a first external supply potential, V
CC
, to a ground potential, V
ss
. When the fabrication of the transistors is completed the N-channel source/drain regions
35
form the emitter, P-substrate
10
forms the base, and the N-well
5
forms the collector of a horizontal parasitic NPN transistor; and the P-channel source/drain regions
60
form the emitter, the N-well
5
forms the base, and the p-substrate
10
forms the collector of a vertical parasitic PNP transistor. The parasitic PNP and NPN bipolar transistors thus formed are actuated by the injection of minority carriers in the bulk of the substrate or the N-well. To prevent latch up, the lifetime of these carriers must be reduced, or the resistance of the substrate must be decreased. The latter method may force compromise in device performance by increasing junction capacitance and body effect.
The N and P substrate ties formed in the related art are gaurdbands which reduce the lifetime of the minority carriers. The gaurdbands act as a sink for the minority carriers that are injected into the substrate or N-well when the emitter/base junction of either parasitic bipolar device is forward biased. The gaurdbands also increase the distance these minority carriers must travel thereby increasing the probability that they will recombine with majority carriers. The gaurdbands are typically formed between the N-channel MOS transistor and the P-channel MOS transistor. The gaurdbands are strips of P+ active regions in the P-substrate and N+ active regions in the N-well. The gaurdbands tie down the substrate and well potentials and prevent latchup by collecting any injected minority carriers from forward biasing the MOS device source or drain regions.
OBJECTS OF THE INVENTION
It is an object of the invention to achieve improved latchup immunity without increasing the complexity of the process steps in a dual-polysilicon process. It is a further object of the invention to reduce the lifetime of the minority carriers, and increase the distance minority carriers must travel to reach a parasitic bipolar collector.
SUMMARY OF THE INVENTION
The invention features a method for forming a trench in an active region of a substrate, and features the trench thus formed. The substrate surface reserved for trench formation is doped to have a first type conductivity. Portions of the substrate are protected, and the substrate is etched in the unprotected areas to form the trench. At the same time the trench is etched a layer overlying the substrate is also etched to form a gate region. Thus, the trench is formed without increasing processing steps. A substrate region at the bottom of the trench is doped to create a substrate region having a second type conductivity. The trench is positioned between a first and second active device and directly in a desired path of the minority carrie
Hoang Quoc
Micro)n Technology, Inc.
Nelms David
Schwegman Lundberg Woessner & Kluth P.A.
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