Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step
Reexamination Certificate
2000-04-10
2001-08-07
Mills, Gregory (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Delaminating processes adapted for specified product
Delaminating in preparation for post processing recycling step
C156S345420
Reexamination Certificate
active
06270622
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a plasma etching process and apparatus for improving the accuracy thereof.
BACKGROUND OF THE INVENTION
A common requirement in integrated circuit fabrication is the etching of openings such as trenches, recesses, contacts and vias in a stack of materials which may include conductive, semiconductive and dielectric materials. The dielectric materials include doped silicon oxide such as fluorinated silicon oxide (FSG), undoped silicon oxide such as silicon dioxide, silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, etc. The dielectric dopants include boron, phosphorus and/or arsenic. The conductive or semiconductive materials include polycrystalline silicon, metals such as aluminum, copper, titanium, tungsten, molybdenum or alloys thereof, nitrides such as titanium nitride, metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, molydenum silicide, etc.
Various plasma etching techniques for etching openings in silicon oxide are disclosed in U.S. Pat. Nos. 5,013,398; 5,013,400; 5,021,121; 5,022,958; 5,269,879; 5,529,657; 5,595,627; 5,611,888; and 5,780,338. The plasma etching can be carried out in medium density reactors such as the parallel plate plasma reactor chambers described in the '398 patent or the triode type reactors described in the '400 patent or in high density reactors such as the inductively coupled plasma reactors described in the '657 patent.
Integrated circuit processing requires tight control over decreasing geometries on increasing wafer size. As a result, monitoring costs in such manufacturing processes have been increasing in spite of the use of in-line monitoring equipment and techniques. As device geometries become smaller, considerable effort has been devoted to improving etching processes for purposes of achieving defect-free integrated circuit structures. See, for example, U.S. Pat. Nos. 5,131,752; 5,362,356; and 5,450,205.
One problem in achieving precise depths during plasma etching processes is due to variation in mask thickness. Such mask thickness variation can result from chemical mechanical polishing (CMP) carried out before the etching process. Although such polishing processes may provide a target thickness for the mask, there will be a certain degree of variation in the masking layer thickness among wafers being processed. In etching processes wherein the target etch depth is controlled by determining etch depth in situ with an interferometer, variation in mask thickness wafer to wafer can contribute to over or under etching of openings such as vias, contacts, trenches, etc. in the layer beneath the masking layer.
It is known to monitor etching process endpoints in plasma chambers by analyzing emissions of substances in the plasma chamber. Typically, as disclosed in, e.g., U.S. Pat. No. 4,615,761, this involves monitoring the quantity of radiation corresponding to a selected one of the plasma reaction products to ascertain when the reaction is finished. U.S. Pat. No. 5,045,149 discloses a method and apparatus for detecting the endpoint of a process of etching a first material over a second material. The optical emission intensity of the plasma etch process is simultaneously monitored by a positive filter and a negative filter generating first and second signals, respectively, the first and second signals being combined to yield a combined signal. The combined signal is monitored for a change indicative of the first material having been etched away and exposing the second material.
U.S. Pat. No. 5,450,205 discloses monitoring etching of a wafer or deposition of a thin film on a wafer by means of a charge coupled device (CCD) camera which views the wafer during plasma processing. Plasma emission or laser illumination reflected from the wafer exhibit temporal modulations caused by interferometry during etching or deposition of the wafer and are used to monitor etching or deposition process endpoints.
U.S. Pat. No. 5,413,966 discloses a trench etch process wherein a trench mask is formed of an upper layer of doped or undoped polysilicon and a lower layer of silicon dioxide or silicon nitride. The two layers are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the underlying silicon substrate. The upper layer is deposited in a thickness corresponding to the depth of the trenches to be etched. The trench etch endpoint is provided by clearing the polysilicon and exposure of the lower layer of the mask. In such a process, variation of the upper layer thickness (e.g., due to variations in deposition process or thickness reducing process such as chemical mechanical polishing) from one wafer to the next in a batch of wafers being processed under identical etching conditions could lead to trenches which are too deep or too shallow for their intended use. Further, if the substrate does not include a stop layer which would allow monitoring of a gaseous species such as by mass spectrometry, in situ measurement and real time control of the etching process to achieve a desired etch depth becomes problematic.
U.S. Pat. No. 5,807,761 discloses a method for real-time and in-situ monitoring for a trench formation process. According to this method, interferometry is used to monitor the etch depth during the etching process. However, use of such a measurement to control the endpoint of etching can lead to inaccurate results since interferometry only provides the etch depth relative to the top of the structure being etched. In the case of etching openings in a masking layer, if the masking layer is etched along with the openings, the measurement of etch depth provided by interferometry, while providing potential for improvement over a timed etch, may not be sufficient to prevent out-of-specification etch depths since compensation for variation in the masking layer thickness prior to etching is not taken into account in the etch depth measurement.
As commercial manufacturing techniques adopt smaller device geometries, it becomes evermore critical to achieve precise etch depths from one wafer to the next during mass production. The prior techniques wherein timed etches were used to achieve a target etch depth are no longer suitable for mass production since even small variations in the actual etch depths relative to the underside of the masking layer can lead to inoperative devices if the openings are too deep or too shallow.
SUMMARY OF THE INVENTION
The invention provides a method of etching openings in a semiconductor substrate in a plasma chamber, comprising steps of supporting a semiconductor substrate on a substrate support in a plasma chamber, the semiconductor substrate including a masking layer and openings in the masking layer containing a material to be etched; etching the material in the openings of the masking layer by generating an etching plasma in the plasma chamber; measuring a thickness of the masking layer prior to completing etching of the material in the openings in the masking layer; controlling duration of the etching step to achieve a target etch depth relative to an underside of the masking layer; extinguishing the etching plasma when the target etch depth of the openings is obtained; and removing the substrate from the chamber.
According to one aspect of the invention, the measuring step can be carried out by interferometry and/or the thickness measuring step can be carried out when a chemical species in the plasma such as silicon chloride or CO is detected. According to another aspect, a layer of material overlying the masking layer is cleared from the masking layer prior to the thickness measuring step. For instance, a layer of material overlying the masking layer can be removed by chemical mechanical polishing prior to the etching step. The method of the invention is advantageous in etching operations wherein the material in the openings does not include a stop layer
Kadavanich Vikorn Martin
Klippert II Walter E
Burns Doane , Swecker, Mathis LLP
Hassonzadeh P.
Lam Research Corporation
Mills Gregory
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