Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-04-16
2004-09-28
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06797620
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the invention described herein relate to a metallization process for manufacturing semiconductor devices and to filling an aperture.
2. Description of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large-scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect apertures formed in high aspect ratio apertures, including contacts, vias, lines, dual damascenes, and other apertures. Reliable formation of these interconnect apertures is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts, dual damascenes, and other apertures, as well as the dielectric materials between them, decrease to less than 250 nanometers, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the apertures, i.e., their height divided by width, increases. Many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), have difficulty filling structures, such as dual damascenes, where the aspect ratio exceed 4:1, and particularly where it exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized apertures having high aspect ratios wherein the ratio of aperture height to aperture width can be 4:1 or higher. Additionally, as the aperture width decrease, the device current remains constant or increases, which results in an increased current density in the aperture.
Currently, copper and its alloys have become the metals of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 &OHgr;-cm compared to 3.1 &OHgr;-cm for aluminum), and a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio apertures, such as a 4:1 aspect ratio via having a width of 0.35&mgr; or less, are limited. As a result of these process limitations, electroplating, which had previously been limited to the fabrication of lines on circuit boards, is just now being used to fill vias and contacts on semiconductor devices.
Electroplating processes deposit a material on a conductive surface by the chemical reduction of metal ions in a chemical solution by the application of an external electrical current. Electroplating processes require a conductive barrier layer being deposited on a substrate surface prior to electroplating to prevent electroplated materials, such as copper, from diffusing into the underlying substrate. Diffusion of electroplated materials, such as copper, into underlying dielectric materials can lead to forming short-circuits or result in device failure. The conductive barrier layer may be deposited by physical vapor deposition techniques or chemical vapor deposition techniques. However, conventional barrier layer materials often do not provide a sufficiently conductive surface for effective electroplating deposition, and a electroplating nucleation or “seed” layer is deposited on the conductive barrier layer to provide sufficient nucleation of electroplating material.
Electroplating processes typically require the electrically conductive seed layer to be thin and conformally deposited on the substrate to provide a surface on the substrate to adequately initiate the electroplating process. The seed layer typically comprises a conductive metal, such as copper, and is conventionally deposited on the substrate using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques. It has been found that conformal deposition of the seed layer results in good electroplating of the substrate.
However, deposition mechanisms for filling apertures using electroplating chemistries have proven difficult to control even with the use conformal seed layers. One mechanism that has been observed when electroplating apertures is known as the “superfill” mechanism, which usually results in the narrowest apertures being filled at an increased rate than wider apertures. As such, excess material, also referred to as overburden or overfill, is deposited over the narrow apertures while the wider apertures are still being electroplated.
A protuberance, or peak, over the narrowest apertures, relative to a depression, or valley, over the wider apertures, can be formed in the surface of the excess material deposited over the apertures. The presence of peaks and valleys in the substrate surface may detrimentally affect subsequent planarization processes, such as chemical mechanical polishing. For example, less than effective planarization of the substrate surface may result in the presence of residual material on the substrate surface. Overpolishing of substrate surface tom remove the residual material materials may result in topographical defects, such as dishing or removal of materials from inside the apertures, which defects can detrimentally affect subsequent processing of the substrate.
Therefore, there is a need for methods for metallizing an aperture with minimal overburden and greater planarization of the substrate surface.
SUMMARY OF THE INVENTION
Aspects of the invention described herein generally relate to depositing materials that inhibit or limit the nucleation or growth of subsequently deposited materials in the apertures to allow for selective fill of apertures formed on the field of a substrate. In one aspect, a method is provided for processing a substrate having a field and an aperture comprising a bottom and sidewalls formed therein, the method including depositing a seed layer on the bottom and sidewalls of the aperture, and depositing a growth-inhibiting layer on at least one of the field of the substrate and an upper portion of the sidewalls of the aperture.
In another aspect off the invention, a method is provided for processing a substrate having a field and an aperture comprising a bottom and sidewalls formed therein, the method including depositing a first copper layer on the bottom and sidewalls of the aperture, depositing a growth inhibiting material selected from the group of silicon dioxide, aluminum, tantalum, nickel, titanium, tungsten, and combinations thereof, on at least one of the field of the substrate and an upper portion of the sidewalls of the aperture, and depositing a second copper layer on the growth inhibiting material and the first copper layer, wherein the second copper layer is deposited on the first copper layer at a greater rate than on the material capable of forming native oxides.
In another aspect off the invention, a method is provided for processing a substrate having a field and an aperture comprising a bottom and sidewalls formed therein, the method including depositing a seed layer on the bottom and sidewalls of the aperture, depositing a growth-inhibiting layer on at least one of the field of the substrate and an upper portion of the sidewalls of the aperture, and depositing a conductive layer on the seed layer at a rate between about 500 angstroms per minute and about 3500 angstroms per minute greater than on the growth-inhibiting layer, wherein at least a portion of the growth-inhibiting layer is removed during deposition of the conductive layer.
In another aspect off the invention, a method is provided for processing a substrate having a field and an aperture comprising a bottom and sidewalls formed therein, the method including depositing a nucleation l
Chen Fusen
Cheung Robin
Dixit Girish
Gandikota Srinivas
Lewis John S.
Applied Materials Inc.
Harrison Monica D.
Moser Patterson & Sheridan
Pert Evan
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