Method and apparatus for implementing two architectures in a...

Details Method and apparatus for implementing two architectures in a... Method and apparatus for implementing two architectures in a...

2008-03-11

2008-03-11

Meonske, Tonia L. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S215000, C712S200000

Reexamination Certificate

active

10602916

ABSTRACT:
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

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Preliminary Search Report issued Feb. 28, 2007 in counterpart foreign application in France under application No. FR 0012031.

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