Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-09-11
2007-09-11
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S097000, C326S098000
Reexamination Certificate
active
11304142
ABSTRACT:
A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.
REFERENCES:
patent: 6429689 (2002-08-01), Allen et al.
patent: 6900666 (2005-05-01), Kursun et al.
Kao Jerry C.
Li Chung-Tao
Storino Salvatore Nicholas
Tretz Christophe Robert
Pennington Joan
Tran Anh Q.
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