Method and apparatus for implementing cache state as history...

Details Method and apparatus for implementing cache state as history... Method and apparatus for implementing cache state as history...

2007-03-20

2007-03-20

Elmore, Stephen C. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000, C711S145000, C711S146000

Reexamination Certificate

active

10251276

ABSTRACT:
A method and apparatus are provided for implementing a cache state as history of read/write shared data for a cache in a shared memory multiple processor computer system. An invalid temporary state for a cache line is provided in addition to modified, exclusive, shared, and invalid states. The invalid temporary state is entered when a cache releases a modified cache line to another processor. The invalid temporary state is used to enable effective optimizations within cache coherent symmetric multiprocessor (SMP) systems of an SMP caching hierarchy with distributed caches with different caching coherency traffic profiles for both commercial and technical workloads.

REFERENCES:
patent: 6263407 (2001-07-01), Arimilli et al.
Jim Handy, The Cache Memory Handbook, 2nded., Academic Press, 1998, p. 44.
Joon-Ho Ha et al, “The SPEED Cache Coherence Protocol for an Optical Multi-access Interconnect Architecture”, Proceedings of the Second International Conference on Massively Parallel Processing Using Optical Interconnections, IEEE, 1995, pp. 98-107.

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