Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-05-07
2002-01-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S097000, C700S100000, C700S101000, C700S102000, C700S103000, C700S121000, C700S213000, C700S120000, C414S936000, C414S937000, C414S939000, C414S940000, C414S941000
Reexamination Certificate
active
06336204
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The invention generally relates to semiconductor wafer processing systems. More particularly, the invention relates to a method and apparatus for handling deadlocks in a multiple chamber semiconductor processing system.
2. Description of the Background Art
Semiconductor wafers are processed to produce integrated circuits using a plurality of sequential process steps. These steps are performed using a plurality of process chambers. An assemblage of process chambers served by a wafer transport robot is known as a multiple chamber semiconductor wafer processing tool or cluster tool.
FIG. 1
depicts a schematic diagram of an illustrative multiple chamber semiconductor wafer processing tool known as the Endura System manufactured by Applied Materials, Inc. of Santa Clara, Calif. Endura is a trademark of Applied Materials, Inc. of Santa Clara, Calif. This tool can be adapted to utilize either single, dual, or multiple blade robots to transfer wafers from chamber to chamber.
The cluster tool
100
contains, for example, four process chambers
104
,
106
,
108
,
110
, a transfer chamber
112
, a preclean chamber
114
, a buffer chamber
116
, a wafer-orienter/degas chamber
118
, a cooldown chamber
102
, and a pair of load lock chambers
120
and
122
. Each process chamber represents a different stage or phase of semiconductor wafer processing. The buffer chamber
116
is centrally located with respect to the load lock chambers
120
and
122
, the wafer orienter/degas chamber
118
, the preclean chamber
114
and the cooldown chamber
102
. To effectuate wafer transfer amongst these chambers, the buffer chamber
116
contains a first robotic transfer mechanism
124
, e.g., a single blade robot (SBR). The wafers
128
are typically carried from storage to the system in a plastic transport cassette
126
that is placed within one of the load lock chambers
120
or
122
. The robotic transport mechanism
124
transports the wafers
128
, one at a time, from the cassette
126
to any of the three chambers
118
,
102
, or
114
. Typically, a given wafer is first placed in the wafer orienter/degas chamber
118
, then moved to the preclean chamber
114
. The cooldown chamber
102
is generally not used until after the wafer is processed within the process chambers
104
,
106
,
108
,
110
. Individual wafers are carried upon a wafer transport blade
130
that is located at the distal end of the first robotic mechanism
124
. The transport operation is controlled by the sequencer
136
.
The sequencer
136
controls the processing and wafer transfer performed by the cluster tool
100
. The sequencer
136
contains a microprocessor
138
(CPU), a memory
140
for storing the control routines, and support circuits
142
, such as power supplies, clock circuits, cache and the like. The sequencer
136
also contains input/output peripherals
144
such as a keyboard, mouse, and display. The sequencer
136
is a general purpose computer that is programmed to perform the sequencing and scheduling operations that facilitate wafer processing and transport. The software routines that control the cluster tool are stored in memory
140
and executed by the microprocessor
138
to facilitate control of the cluster tool.
It is contemplated that some of the process steps discussed herein as software processes may be implemented within hardware, e.g., as circuitry that cooperates with the microprocessor to perform various process steps. Although the schedule generator is depicted as a general purpose computer that is programmed to perform various scheduling routines, the processes that are implemented by the software can be implemented as hardware as an application specific integrated circuit (ASIC) or discrete circuit components. As such, the process steps described herein are intended to be broadly interpreted as being equivalently performed by software, hardware, or any combination thereof.
The transfer chamber
112
is surrounded by, has access to, the four process chambers
104
,
106
,
108
and
110
, as well as the preclean chamber
114
and the cooldown chamber
102
. To effectuate transport of a wafer amongst the chambers, the transfer chamber
112
contains a second robotic transport mechanism
132
, e.g., another single blade robot (SBR). The mechanism
132
has a wafer transport blade
134
attached to the distal end of an extendable arm. The blade is used for carrying the individual wafers to and from a chamber.
Once processing is complete within the process chambers, the transport mechanism
132
moves the wafer from the process chamber and transports the wafer to the cooldown chamber
102
. The wafer is then removed from the cooldown chamber using the first transport mechanism
124
within the buffer chamber
116
. Lastly, the wafer is placed in transport cassette
126
within the load lock chamber
122
.
When considering the effects of a deadlock, a system is assumed to consist of a finite number of resources (e.g., CPU, memory, printers, chambers, robots, load locks, and the like) to be distributed among a number of competing entities (e.g., processes, wafers, and the like). The resources are assumed partitioned into several types, each type being comprised of a certain number of identical instances. For example, if a cluster tool has a stage with two parallel etch chambers, then the resource type “etch” has two instances. Thus, if an entity requests some resource type, the allocation of any instance of that type must satisfy the request.
A deadlock situation arises when no further progress can be made due to inadequate scheduling of activities in the system (i.e., a resource misallocation). Let {W
1
, W
2
, . . . , W
n
} be a set of entities (e.g., wafers) operating on a set of resources {C
1
, C
2
, . . . , C
k
} and let k
i
be a non-empty subset of {C
1
, C
2
, . . . , C
k
} the entity W
i
must acquire in order to finish its task. Then, W
1
, W
2
, . . . , W
n
are in a “deadlock state” if K
i
is held by entities other than W
i
for all i. In other words, a set of entities is in a deadlock state when every entity is waiting for an event (e.g., resource release) that can only be caused by another entity from the same set. Consequently, a deadlock problem is a logical one and it happens when members of a group of entities which hold resources are blocked indefinitely from access to resources held by other entities within the group. When no entity in the group will relinquish control over its resources until after it has completed its current resource acquisition, deadlock is inevitable and can be broken only by the involvement of some external agency.
A deadlock in a cluster tool may cause substantial processing delays that could result in wafer damage. Poor handling of a deadlock state in a cluster tool may cause a significant loss of throughput which directly translates into the loss of money for integrated circuit manufacturers.
Therefore, a need exists in the art for a method and apparatus that efficiently handles deadlocks in multiple chamber cluster tool to improve throughput of the tool.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for handling deadlocks in a multichamber semiconductor wafer processing system known as a cluster tool. The invention is embodied in a plurality of software routines that execute upon a sequencer of a cluster tool. The invention performs deadlock avoidance, deadlock detection and deadlock resolution towards achieving optimal wafer throughput for a cluster tool.
In one embodiment of the invention, the sequencer executes a deadlock avoidance routine that ensures that wafer deadlock never occurs by first identifying a wafer processing loop within the wafer process sequence. A wafer processing loop occurs in a process sequence when a particular chamber in the sequence must be used for two process steps. As such, a wafer progresses through a plurality of chambers and loops back to a chamber (known as a knot chamber) that had already been us
Applied Materials Inc.
Smith Matthew
Thomason Moser & Patterson
Thompson A. M.
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