Method and apparatus for handling data transfers

Details Method and apparatus for handling data transfers Method and apparatus for handling data transfers

2005-05-10

2005-05-10

Elmore, Stephen (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S100000, C711S154000, C711S171000, C710S010000, C369S030010, C369S047100

Reexamination Certificate

active

06892274

ABSTRACT:
Embodiments of the present invention provide for implementation of data transfers in an efficient manner. The 48-bit LBA mechanism requires two sets of I/O writes to IDE registers on primary channel or secondary channel. The two sets of I/O writes to the primary or secondary channel registers are performed by setting a status register to a first or second state appropriately depending on the data. Embodiments of the present invention provide a single set of writes to I/O registers when the size of the data transfer is equal to or below a threshold value.

REFERENCES:
patent: 5854942 (1998-12-01), Penokie
patent: 5909592 (1999-06-01), Shipman
patent: 6502212 (2002-12-01), Coyle et al.
patent: 6557058 (2003-04-01), Jackson
patent: 6718401 (2004-04-01), Nalawadi et al.
patent: 6789163 (2004-09-01), Fox et al.
patent: 20010001870 (2001-05-01), Ofek et al.
patent: 20030056059 (2003-03-01), Fox et al.

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