Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-07
2009-02-24
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000, C714S725000, C714S726000, C714S727000, C714S025000, C714S724000, C714S741000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S015000, C703S020000
Reexamination Certificate
active
07496820
ABSTRACT:
Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.
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Edmondson Walter H.
Simmons Michael L.
Statovici Mihai G.
Theron Conrad A.
Brush Robert M.
Trimmings John P
Xilinx , Inc.
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