Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-19
2007-06-19
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S727000, C714S731000, C714S744000
Reexamination Certificate
active
10651168
ABSTRACT:
The present invention is directed to an improved method, system and apparatus for self-testing an electronic device. A scan latch used in a multi-cycle bus is uniquely operated to generate signal transitions consistent with the normal operating speed of the device. This occurs even when a normal signal transition would not otherwise occur since the multi-cycle bus normally requires a plurality of clock pulses to create such signal transition. The logical states of master and slave clocks associated with test scan logic are used to automatically cause the output of a scan latch to invert its output or switch from its previous state at each rising edge of the slave clock that is not preceded by a master or scan clock. This ensures transitions will appear at the output of the latch consistent with the operating clock speed of the slave clock, and these transitions are detected during an AC test of the device to determine the maximum operation frequency of the device even when the device contains an internal multi-cycle bus.
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Bailey Wayne P.
De'cady Albert
Salys Casimer K.
Siddiqui Saqib J.
Yee Duke W.
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