Method and apparatus for generating DMA transfers to memory

Details Method and apparatus for generating DMA transfers to memory Method and apparatus for generating DMA transfers to memory

2010-01-29

2011-10-04

Kindred, Alford (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S001000

Reexamination Certificate

active

08032670

ABSTRACT:
In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

REFERENCES:
patent: 5075846 (1991-12-01), Reininger et al.
patent: 5404522 (1995-04-01), Carmon et al.
patent: 5634069 (1997-05-01), Hicok et al.
patent: 5640399 (1997-06-01), Rostoker et al.
patent: 5825774 (1998-10-01), Ready et al.
patent: 5978866 (1999-11-01), Nain
patent: 5983301 (1999-11-01), Baker et al.
patent: 6038629 (2000-03-01), Ogilvie
patent: 6070182 (2000-05-01), Rao et al.
patent: 6209046 (2001-03-01), Sato et al.
patent: 6874040 (2005-03-01), Gregg
patent: 6948010 (2005-09-01), Somers et al.
patent: 7089335 (2006-08-01), Aiken et al.
patent: 7089344 (2006-08-01), Rader et al.
patent: 7139848 (2006-11-01), Murray et al.
patent: 7254651 (2007-08-01), Rozario et al.
patent: 7260688 (2007-08-01), Baxter
patent: 7386642 (2008-06-01), Inoue et al.
patent: 7496695 (2009-02-01), Go et al.
patent: 2003/0097498 (2003-05-01), Sano et al.
patent: 2004/0064600 (2004-04-01), Lee et al.
patent: 2004/0068590 (2004-04-01), Nishino
patent: 2005/0060441 (2005-03-01), Schmisseur
patent: 2006/0009695 (2006-01-01), Matthew et al.
patent: 2006/0015748 (2006-01-01), Gato et al.
patent: 2007/0022225 (2007-01-01), Nair et al.
patent: 2010/0064069 (2010-03-01), Shasha
patent: 99/14680 (1999-03-01), None
patent: 0235368 (2002-02-01), None
patent: 2004/010314 (2004-01-01), None
U.S. Appl. No. 11/238,790, filed Sep. 29, 2005.
James B. Keller, “The PWRficient Processor Family,” PA Semi, Oct. 2005, 31 pages.
U.S. Appl. No. 11/238,850, filed Sep. 29, 2005.
Office Action in U.S. Appl. No. 11/238,790 mailed Apr. 15, 2008.
Response to Office Action in U.S. Appl. No. 11/238,790, filed Jun. 24, 2008.
ARM Limited: “PrimeCell Single Master DMA Controller (PL081);” Revision r1p1, Feb. 2003, 90 pages.
IBM: “DMA Slave Data Security,” Technical Disclosure Bulletin, vol. 34, No. 12, May 1, 1992, p. 327, XP002423605; 90 pages.
Office Action from U.S. Appl. No. 11/620,875 mailed Jul. 24, 2008.
Response to Office Action from U.S. Appl. No. 11/620,875, filed Oct. 15, 2008.
Office Action from U.S. Appl. No. 11/238,850 mailed Jul. 21, 2008.
Response to Office Action from U.S. Appl. No. 11/238,850, filed Oct. 15, 2008.
Office Action from U.S. Appl. No. 11/238,790 mailed Oct. 14, 2008.
Office Action from U.S. Appl. No. 11/682,051 mailed Oct. 6, 2008.
Response to Office Action from U.S. Appl. No. 11/238,790, filed Dec. 1, 2008.
Office Action from U.S. Appl. No. 11/238,850 mailed Dec. 31, 2008.
Office Action from U.S. Appl. No. 11/620,875 mailed Jan. 8, 2009.
“Microsoft Computer Dictionary,” 2002, Microsoft Press, 5th Edition, p. 335.
Response to Office Action from U.S. Appl. No. 11/238,790, filed Dec. 1, 2008.
Office Action from U.S. Appl. No. 11/682,051 mailed Mar. 17, 2009.
Communication pursuant to Article 94(3) EPC, App No. 06815807.0-2212, dated Jun. 16, 2010.
Office action in U.S. Appl. No. 12/564610 issued Dec. 3, 2010.
Japanese Abstract and Publication for Patent No. JP10187593, dated Jul. 21, 1998, 16 pages. (includes partial translation).
Office Action from Japanese Patent Application No. 2008-533662, dated Apr. 20, 2011, 5 pages.
Japanese Abstract and Publication for Patent No. JP10334040, dated Dec. 18, 1998, 30 pages. (includes partial translation).
Japanese Abstract and Publication for Patent No. JP63137351, dated Jun. 9, 1988, 5 pages. (includes partial translation).

Affiliated with

Also associated with

Rating

Method and apparatus for generating DMA transfers to memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for generating DMA transfers to memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for generating DMA transfers to memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4295996