Method and apparatus for frequency independent processor...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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Reexamination Certificate

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07870406

ABSTRACT:
Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit (60) is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit (60) changes.

REFERENCES:
patent: 6549930 (2003-04-01), Chrysos et al.
patent: 7472390 (2008-12-01), O'Connor et al.
patent: 7707578 (2010-04-01), Zedlewski et al.
patent: 2001/0056456 (2001-12-01), Cota-Robles
patent: 2004/0216120 (2004-10-01), Burky et al.
patent: 2005/0210472 (2005-09-01), Accapadi et al.

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