Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
2000-08-03
2002-12-31
McDonald, Rodney G. (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S192150, C204S192170, C204S298060, C204S298110, C118S7230AN, C118S7230IR, C156S345480, C427S569000, C427S576000, C438S597000, C438S652000, C438S656000, C438S685000
Reexamination Certificate
active
06500315
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacturing and more particularly to methods for forming layers on a semiconductor substrate using physical vapor deposition.
BACKGROUND OF THE INVENTION
Ionized metal plasma physical vapor deposition (INP-PVD) is commonly used to deposit conductive metal and metal-containing films onto semiconductor substrates. It is particularly useful for forming layers within high aspect ratio openings. A cross-section illustrating portions of a typical IMP-PVD chamber design is shown in FIG.
1
. The cross-section includes a chamber
10
, a sputtering target
12
, a shield
14
, a coil
16
, a pedestal
18
, and a semiconductor substrate
19
. During normal operation, the target
12
is biased such that ions from a plasma are accelerated towards the target, whereby they strike it and “sputter” atoms off of the target and onto the substrate
19
, thereby forming a layer on the substrate
19
. The coil
16
provides a variety of functions during the IMP-PVD deposition process including generating ions that sputter the target
12
, heating electrons in the plasma so they can more efficiently ionize gas molecules, and additionally, ionizing atoms sputtered from the target and providing an additional sputtering source for depositing material onto the substrate.
FIG. 2
includes a top-down view of the IMP-PVD chamber shown in
FIG. 1
illustrating portions of the shield
14
, the coil
16
, and the semiconductor substrate
10
. Additionally included in
FIG. 2
are ceramic support pins
22
, which electrically insulate the coil
16
and the shield
14
, and ceramic feed through pins
24
. In addition to electrically insulating the coil
16
and the shield
14
, the ceramic feed through pins
24
serve as conduits for electrically coupling the coil
16
to an external power source. Additionally, the ceramic support pins
22
and feed through pins
24
physically support the coil
16
in the chamber and are the coil's primary heat transfer agent (i.e. the primary source for dissipating heat generated by the coil) during the deposition process. Prior art IMP-PVD chambers that utilize coils and ceramic pins
22
and
24
may be adequate for low coil power applications (less than 2.5 kilowatts), however they may not be suitable for higher coil power applications (greater than 2.8 kilowatts).
Increasing the power applied to the coil has been found to have a number of processing advantages. Increasing the coil power increases the number of ionized species available at the substrate surface, which can improve the step coverage and uniformity of the layer being deposited. This can be particularly useful for depositing films such as copper films and copper barrier films into high aspect ratio openings. In addition, the increased coil power increases the overall deposition rate, which has the potential for increasing process throughput and providing additional process control. However, increasing the power applied to the coil using the prior art chamber configuration can also negatively impact processing because the increase in power can uncontrollably heat the coil. This can undesirably affect the deposition process and negatively impact the mechanical integrity of the coil. The uncontrolled changes in the coil temperature can influence the grain size and sputter rate of the coil's material and correspondingly produce uncontrolled changes in the uniformity and step coverage of the deposited film. This necessitates using throughput-limiting cooling steps during deposition process to prevent coil overheating. Finally, the prior art ceramic pin chamber configuration may be insufficient for controlling or preventing electrical coupling between the coil
16
and the shield
14
which can become problematic at higher coil powers
REFERENCES:
patent: 3935412 (1976-01-01), McDonough et al.
patent: 5680013 (1997-10-01), Dornfest
patent: 5707498 (1998-01-01), Ngan
patent: 5716451 (1998-02-01), Hama et al.
patent: WO 97/42648 (1997-11-01), None
Rossnagel et al., “Directional dna Ionized Sutter Deposition for Microelectronics Applications,” Proc. of the 3rd ISSSP, Tokyo, pp. 253-260 (1995).
Arnold John C.
Arunachalam Valli
Denning Dean J.
Ventzek Peter L. G.
McDonald Rodney G.
Motorola Inc.
Rodriguez Robert A.
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