Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1998-11-05
2001-04-24
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S217000, C712S023000
Reexamination Certificate
active
06223278
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the execution of instructions in a computer processor, and, more particularly, to a method and apparatus for floating point (FP) status word handling in an out-of-order (OOO) processor pipeline.
2. Description of the Related Art
With the increasing complexity of computer applications to meet the demands of the computer user, the number of instructions to be carried out by a computer's processor is significantly increasing as well. Accordingly, with the growing number of instructions to be carried out, it is desirable to execute these instructions in the most expedient manner possible in order to optimize system performance.
Floating point (FP) instruction sets, when executed in a processor pipeline, include a status word (FPSW) that contains information regarding the execution of older instructions, and is used to make decisions for future flow of instructions within the processor pipeline. The status information provided by the FPSW is “sticky” in nature, i.e., it is the sum of the execution of all previous instructions. However, in an out-of-order (OOO) processor pipeline, where these FP instructions are executed out-of-order, determining the status of these instructions becomes more complicated.
A simplistic approach to solve this problem is to add additional micro-code to each FP instruction to explicitly create a status word. However, this approach is not an optimal solution, especially since the status is sticky and will increase the number of micro-instructions (micro-ops) executed within the pipeline (even though there may not be a need for the information contained in the status word). Thus, this approach would increase the number of micro-instructions handled by the processor pipeline, thus decreasing the efficiency of the pipeline.
Another approach may be to block the reading of the status word at the instruction renamer unit until all earlier micro-instructions have retired. However, if such an approach is taken, it would directly affect the amount of time for the execution of these instructions, since all future activity is waiting on such execution. Thus, this approach will also impede the execution of these instructions, thereby decreasing the performance of the processor pipeline.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method for performing floating point (FP) instruction handling is provided. A floating point store status word (FSTSW) instruction is inserted within a plurality of micro-ops corresponding to a plurality of FP instructions and the plurality of micro-ops are ordered for execution.
In another aspect of the present invention, a processor is provided for executing a plurality of floating point (FP) instructions. The processor includes a fetcher/decoder unit to retrieve a plurality of FP instructions from a memory structure and generate a plurality of micro-ops from the FP instructions. The processor further generates a floating point store status word (FSTSW) instruction and includes a scheduler unit to re-order the micro-ops for execution.
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patent: 5826070 (1998-10-01), Olson et al.
patent: 6021488 (2000-01-01), Eisen et al.
patent: 6032249 (2000-02-01), Olson et al.
patent: 6061786 (2000-05-01), Witt
Blakely , Sokoloff, Taylor & Zafman LLP
Donaghue Larry D.
Intel Corporation
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