Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-02-16
2003-04-15
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
06550033
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of network communications, and more particularly, to the testing of an external system memory of a network interface controller.
BACKGROUND OF THE INVENTION
Network interface controllers handle the transmission and reception of frame data between a transmitting network station and a receiving network station via a network communications system, such as a local area network. For transmission, frame data is sent from an upper layer down through a driver layer, a media access controller layer and then to a physical layer. In the transmitting network station, a central processor unit writes frame data and associated descriptors into system memory where a network interface controller reads the frame data and transmits the frame data onto the network. At the receiving network station a network interface controller stores the frame data into memory.
Clock speed and data transfer rates differ between the network and system sides of the network interface controller. Therefore, it is necessary to incorporate some quantity of data storage within the network interface controller. In some applications, it is advantageous for the network interface controller to incorporate a large amount of storage. The desired memory size may exceed that which can practically be integrated in a single-chip design, requiring external memory and an associated interface. This external memory, along with the PC board traces and connections, as well as parts of the logic within the network controller, comprise a memory subsystem. Failures in the memory subsystem may result from electrical or mechanical failure of any of the elements of the system and/or errors in the design of the PC board such as excessive loading or trace length.
Traditionally, register based read/write tests have been employed to test memory subsystems. However, register based read/write tests do not sufficiently test a memory subsystem. This is because the subsystem is not tested as a unit at normal operating speed to verify its correct operation. Furthermore, the register access logic provides a complication to the testing of the memory interface within the controller.
Additionally, it is desirable to determine the size of the memory through diagnostic software in order to allow different size memories to be connected to the network interface controller.
SUMMARY OF THE INVENTION
There is a need for a method and apparatus for testing the external memory of a network controller at normal operating speed in order verify correct operation.
These and other needs are met by embodiments of the present invention which provide a network interface controller coupled to an external memory. The controller comprises an external memory interface that interfaces the external memory to the network interface controller. The controller also includes memory built-in self-test (MBIST) logic configured to test an external memory coupled to the external memory interface, at a normal operating speed of the external memory.
The provision of MBIST logic in the network interface controller used to test the external memory at its normal operating speed allows the external memory to be checked sufficiently to verify correct operation. This overcomes the imitations of conventional register based read/write tests that do not sufficiently test the memory subsystem. Furthermore, the register access logic of the network interface controller is not used as part of the memory interface within the controller during the MBIST.
When the network interface controller is provided with a memory size register, in accordance with certain embodiments of the invention, running the MBIST test with different sizes allows the actual size of the memory to be determined in an elegant manner.
The earlier stated techniques are also met by another embodiment of the present invention which provides a method of testing the memory subsystem of a network interface coupled to an external memory. The method comprises the steps of setting a memory size register with a memory size value, performing a memory built-in self-test (MBIST), re-setting the memory size register with a different memory size value, re-performing the MBIST, and repeating the steps of re-setting the memory size register and re-performing the MBIST until the external memory size is determined.
REFERENCES:
patent: 4974236 (1990-11-01), Gurcan et al.
patent: 5508752 (1996-04-01), Kim et al.
patent: 5512957 (1996-04-01), Hulyalkar
patent: 5801595 (1998-09-01), Davis et al.
patent: 5949878 (1999-09-01), Burdge et al.
patent: 5974579 (1999-10-01), Lepejian et al.
patent: 6044481 (2000-03-01), Kornachuk et al.
patent: 6151692 (2000-11-01), Smitlener et al.
patent: 6237123 (2001-05-01), Kim et al.
Nadeau-Dostie et al., Serial interfaceing for embedded-memory testing, IEEE, p. 52-63, 1990.*
International Search Report for PCT/US00/04080, filed Feb. 17, 2000.
Advanced Micro Devices , Inc.
Chase Shelly A
De'cady Albert
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