Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Patent
1998-02-02
2000-05-16
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
G06F 112
Patent
active
060651261
ABSTRACT:
A self-timed and self-enabled distributed clock is provided for a functional unit that has variable executing time. The self-timed clock provides plurality of clock pulses within a clock cycle for latching of result and starting execution of the next operation. The functional unit can execute more than one operation per clock cycle thus increasing the utilization of the execute unit and the performance of the processor. The state machine is designed to keep track of the current clock pulse and the execution time of the current operation. The functional unit includes the output queue buffer to keep plurality of results from execute unit. The functional unit executes data close to its optimal timing while the data between functional units are synchronized on the clock boundary as in synchronous design. It is more efficient than synchronous design yet the outputs are deterministic as the clocking is preserved in the design.
REFERENCES:
patent: 5774699 (1998-06-01), Nagae
patent: 5901322 (1999-05-01), Herbst et al.
patent: 5987620 (1999-11-01), Tran
Mahalingaiah Rupaka
Tran Thang Minh
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