Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-02-08
2001-02-13
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S037000, C216S059000, C438S009000, C438S694000, C438S714000, C438S719000, C438S723000, C156S345420
Reexamination Certificate
active
06187685
ABSTRACT:
This invention relates to a method and apparatus for plasma etching a feature in a substrate, for example a semiconductor substrate, in particular, although not exclusively, to a method of reducing or eliminating localised etching of the substrate (“notching”) or charge damage at the interface with an insulating underlayer.
When etching silicon (or any other material), which becomes isolated by an insulating underlayer (such as silicon dioxide), the silicon accumulates charge as a result of the current drawn from the plasma during the process. This volume charge is proportional to the current, the surface area and the thickness of silicon above the oxide layer. The other factor which needs to be considered is that of the surface charge component on the silicon and the oxide. As this charge increases, it can have a proportionately increasing influence on the ion trajectory angle, which in turn influences the silicon etch profile, particularly at the silicon to oxide interface. The net result of excessive ion charging is localised etching of the silicon or “notching” at the oxide interface. It has been found that, if the oxide (or other dielectric) layer is replaced by a conducting layer, then the “notching” is not observed.
In some applications, this notching is highly undesirable, either due to causing problems in post processing steps (such as the re-fill of silicon isolation trenches), or due to the impact of the profile deterioration on the device performance.
A number of solutions to this problem have been proposed. Most are based on methods of either “neutralising” the accumulated surface charge, or reducing the ion charging of the silicon directly. For example, Toshihisa Nozawa et al (1994 Dry Process Symposium, Tokyo, I-8, p37ff) refers to the reduction of ion charging by operating at relatively higher pressures so that an increase in the negative ion concentration results in “neutralisation” of the accumulated surface charge. Whilst this method has been used with some success, operating at these pressures does cause some restrictions with respect to the etched profile such that it is not a suitable application for the entire etch. Indeed, the approach of using relatively higher pressures can only be used as a second etch step to approach the silicon interface, before the silicon begins to etch clear of the oxide interface.
Morioka et al, J. Vac. Sci. Technol. A 16(3), May/June 1998, pp 1588-1593 discloses the use of lower frequency to reduce notching and charge damage.
Kinoshita et al “Simulation of Topography Dependent Charging with Pulse Modulated Plasma”, Proc.Sym. On Dry Process, Vol.18, I-6, pp 37-42, 1996 discloses source pulsing using continuous wave (CW) bias to achieve notch and charge damage reduction or elimination.
The theory of source pulsing reducing notching relates to the bias reduction as a result of the after-glow plasma during the off state, see Kinoshita et al. This approach works very well for low pressure HDP processing and as such it has inherent limitations. The major drawback is that the method only works when the plasma completely extinguishes. The plasma essentially comprises two excitation components, the first results from the source (ICP,ECR etc) and the second results from the RF bias. These two components control the plasma density and self bias potential for ion acceleration respectively. When the source power is reduced, the self bias increases proportionately. Thus, when the source power is off, extremely high self bias voltages are obtained until or unless the plasma extinguishes. If the plasma does extinguish (which is certainly valid for low pressure and low bias power operation, cited in the prior art references including Kinoshita), source pulsing is an effective solution. However, for relatively higher pressure plasmas (approaching or greater than 10 mTorr), the plasma does not extinguish, even at low bias RF power levels. In such cases the source pulsing method is not suitable.
During source power switching with CW RF bias, for the reasons explained above, as the source power switches off, high self bias transient voltages are inevitable. These transients may lead to charge damage. As the source power levels increase (to enhance the etching rate), this effect will increase and potentially cause unacceptable charge damage and possibly even increased notching.
Maruyama et al, “Reduction in charge build-up with pulse-modulated bias in pulsed ECR plasma”, IEE Proc. Dry Process Sym. Japan, I-4 pp 21-26, 1997 discloses the use of a pulsed bias at 13.56 MHz (high frequency), but reports a residual notch size of at least 70 nm in the best case.
The method of this invention, in at least some embodiments, addresses or reduces these various problems.
According to a first aspect of the present invention, there is provided a method of etching a feature in a substrate in a chamber, the method comprising alternately etching by means of a plasma and depositing a passivation layer by means of a plasma, wherein a bias frequency is applied to the substrate which is at or below the ion plasma frequency.
The bias frequency may or may not be pulsed.
According to a second aspect of the present invention, there is provided a method of etching a feature in a substrate in a chamber, the method comprising alternately etching by means of a plasma and depositing a passivation layer by means of a plasma, wherein a pulsed bias frequency is applied to the substrate.
In this aspect of the invention a high or low bias frequency may be applied.
According to a third aspect of the present invention, there is provided a method of etching a feature in a substrate in a chamber by means of a plasma, the method comprising applying a pulsed bias frequency to the substrate which is at or below the ion plasma frequency.
The ion plasma frequency is represented by &ohgr;
pi
.
The bias frequency may be produced by an rf or dc bias power supply, and is preferably applied to a support or platen on which the substrate may be positioned. A dc bias which is pulsed is particularly suitable if the substrate is sufficiently conducting or is of a form where most of the material is conducting but a thin insulating layer may exist within the structure. The dc bias may be pulsed in conjunction with CW or pulsed rf bias.
The substrate is preferably a semiconductor, for example silicon. In a particular embodiment, the substrate comprises an insulating underlayer. This underlayer may be an oxide. In the embodiment in which silicon is used as the semiconductor, silicon dioxide is the underlayer. However, for example, the invention also relates to etching polysilicon and other conductors (eg WSi
2
or indeed other metal silicides) over gate oxide. Alternatives are well known to a person skilled in the art.
By using a low bias frequency, reduced “notching” or charge damage may be achieved. In a preferred embodiment, the bias frequency is at or below 4 MHz, and even more preferably is in the range of 50 kHz to 380 kHz.
The method may comprise a further etching and passivating step (step 2) which is carried out at a higher pressure than the etching or alternate etching and deposition step. This further step may or may not be alternately cyclic. In particular, this further step which is carried out at a higher pressure is started when the underlayer is approached, for example in one embodiment either just before or any time up to just after the silicon begins to etch clear from the oxide interface.
For example, when etching thick silicon (>several microns) on the insulator then step 1 is used until critical features have approximately 0.5 &mgr;m of silicon remaining to be etched, at the substrate edge. The edges etch faster than the substrate centre. At the centre there is approximately 1 &mgr;m silicon remaining to be etched. Step 2 is then used until the oxide is reached at all points of the substrate and a sufficient over etch may be used to ensure this.
This further etching and passivation step provides a reduction in the rate of increase in the notch size as a function of over-etch time
Ashraf Huma
Bhardwaj Jyoti Kiron
Hopkins Janet
Hynes Alan Michael
Johnston Ian Ronald
Jones Volentine, LLC
Powell William
Surface Technology Systems Limited
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