Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-09-11
2009-08-11
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S027000
Reexamination Certificate
active
07574639
ABSTRACT:
A method and an apparatus for entering special mode in integrated circuit (IC) or logic circuit are provided. The IC or logic circuit receives a plurality of data bits and a reset signal, wherein the reset signal is used to reset the IC or the logic circuit. The apparatus includes a plurality of registers and a logic circuit. The registers receive the data bits and the reset signal and output the data bits when the reset signal is transferred from a second state to a first state. The logic circuit includes a logic output terminal and a plurality of logic input terminals, wherein the logic input terminals are coupled to the registers respectively and receiving the data bits output from the registers. When the logic input terminals receive a predetermined value, the logic value output from the logic output terminal is transferred to enter the special mode.
REFERENCES:
patent: 5259006 (1993-11-01), Price et al.
patent: 5826007 (1998-10-01), Sakaki et al.
patent: 6874069 (2005-03-01), Lin et al.
patent: 7058756 (2006-06-01), Park
Hsu Shih-Pin
Hung Ching-Ho
Jianq Chyun IP Office
Kerveros James C
Novatek Microelectronics Corp.
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