Method and apparatus for ensuring data consistency between an i/

Details Method and apparatus for ensuring data consistency between an i/ Method and apparatus for ensuring data consistency between an i/

1998-06-29

2000-08-22

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 24, 710 26, 710 33, 710 55, 714141, 714142, 714143, 714144, G06F 1300

Patent

active

061087211

ABSTRACT:
In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coherency and then responds back only after coherency has been ensured. Specifically, a DMA.sub.-- SYNC transaction is broadcast to all I/O channels in the system. Responsive thereto, each I/O channel writes back to memory any modified lines in its cache that might contain DMA data for a DMA sequence that was reported by the system as completed. The I/O channels have a reporting means to indicate when this transaction is completed, so that the DMA.sub.-- SYNC transaction does not have to complete in pipeline order. Thus, the I/O channel can issue new transactions before responding to the DMA.sub.-- SYNC transaction.

REFERENCES:
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5778437 (1998-07-01), Baylor et al.
patent: 5796979 (1998-08-01), Arimille et al.
patent: 5890217 (1999-03-01), Kabemoto et al.
patent: 5918070 (1999-06-01), Moon et al.
patent: 6003106 (1999-12-01), Fields, Jr. et al.

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