Method and apparatus for enhanced parallel port JTAG interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reexamination Certificate

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07039839

ABSTRACT:
A method and apparatus for an enhanced parallel port JTAG interface (IEEE Test Access Port) that includes a clock signal line where the clock signal line is a delayed and inverted version of a data strobe signal line. A data input signal line, a data output signal line, a mode select signal line, and a wait signal line are also include. The wait signal line is a delayed and inverted version of the data strobe signal line. The enhanced JTAG cable is connectable between an Enhanced Parallel Port (EPP) and a JTAG port and has increased performance over using a Standard Parallel Port (SPP).

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patent: 6813674 (2004-11-01), Velasco et al.
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, (IEEE Std. 1149.1-2001), Test Technology Standards Committee of the IEEE Computer Society, (2001), 208 pgs.
“Intel™ System Architecture”,PXA250and PXA210 Application Processors Developer's Manual, 2-1 through 3-1, 41 pgs.
“Warp Nine Engineering: EPP Mode”, http://www.fapo.com/eppmode.htm, (Observed Apr. 2, 2002), 4 pgs.

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