Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-12-28
2004-11-09
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S045000
Reexamination Certificate
active
06816989
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the debugging of digital logic devices. More specifically, the present invention relates to the retrieval of state data and program counter data from a digital logic device. Still, more particularly, the invention relates to a digital logic device that includes a port for off-loading test data generated at or near the normal clock speed of the digital logic device to an external device operating at a slower speed.
2. Background of the Invention
The design and development of digital logic circuits has become increasingly complex, due in large measure to the ever-increasing functionality offered in such circuits. Integrated circuits are constantly surpassing milestones in performance, as more and more functionality is packaged into smaller sizes. This enhanced functionality requires that a greater number of transistors be included in an integrated circuit, which in turn requires more rigorous testing to insure reliability once the device is released. Thus, integrated circuit designs are repeatedly tested and debugged during the development phase to minimize the number and severity of errors that may subsequently arise. In addition, chips may be tested to determine the performance characteristics of the device, including the speed or throughput of the chip, software running on the chip, or the aggregate performance of the system.
As integrated circuits become more complex, the length of the debug phase increases, requiring a greater advanced lead-time before product release. In addition, as the complexity of integrated circuits increase, it becomes necessary to fabricate more prototype iterations of the silicon (or “spins” of silicon) in order to remove successive layers of bugs from the design, thereby increasing the engineering and materials cost of the released product. It would be desirable to reduce these engineering and material costs and speed up the product cycle. Moreover, if more data, or more accurate data was available for analysis, the designers and debuggers might be able to expedite the design and debug process for the product, thereby minimizing the number of spins and the time to release the product.
One of the chief difficulties encountered during the debug phase of a product is identifying the source of an error. This can be extremely difficult because the error may make it impossible to obtain state information from the integrated circuit. For example, in a processor, an error may cause the processor to quit executing, thus making it impossible to obtain the state data necessary to identify the source of the error. As a result, the debug process requires that the debug team infer the source of the error by looking at memory accesses by the processor or patterns of activity on other external busses. The normal technique for probing external busses is to solder a wire onto a terminal or trace. Unfortunately, merely adding a soldered wire to a terminal or trace can create signal reflections, which may distort the data being monitored. Thus, the manual probing of bus terminals and traces is impractical and inaccurate, especially those attached to high speed, highly complex chips. More sophisticated techniques are also used, but are expensive and suffer, albeit to a lesser degree, from the same effects. Further, because the state information available on these busses is typically a small subset of the processor's state, the debug team must make guesses regarding the state of data internal to the processor. If the internal state of the processor could be acquired and stored, these inferences would be replaced by solid data. By reducing the designer's uncertainty and increasing the available data, this would be beneficial in solving problems with the processor hardware or software.
In certain products under development, such as new microprocessors under development by the assignee of the present invention, the number of transistors is exceedingly large and their dimensions are exceedingly small. Both of these factors make it practically impossible to probe internal terminals of the chip or internal wire traces. Moreover, to the extent that certain internal terminals and traces could be probed, the conventional methods for conducting such a probing operation are extremely expensive, and some might potentially corrupt the state of the terminals and traces being probed. Consequently, the only common technique currently available to test or probe the state of terminals and traces in highly complex chips is to route signals through the chip's external output terminals, to some external interface. This approach, as presently implemented, suffers in certain respects.
Oftentimes the internal clock rate of the chip operates at a much higher rate than the external logic analyzers that receive and process the data. As an example, processor designs currently under development operate at clock speeds up to and exceeding 2.0 GHz. The fastest commercial logic analyzers, despite their expense, are incapable of operating at GHz frequencies. Thus, either certain data must be ignored, or some other mechanism must be employed to capture the high-speed data being generated on the chip. The typical approach is to run the chip at a slower clock speed so the data can be captured by external test equipment. This solution, however, makes it more difficult to detect the bugs and errors that occur when the chip is running at full clock speeds. Some errors that occur at full clock speed will not be detected when the clock speed is reduced to accommodate the off-chip logic analyzers. Also, increasingly the processor connects to external components that have a minimum speed, below which they will not operate. These speeds require the processor to operate faster than the external logic analyzer can accommodate.
The assignee of the present invention has developed a specially dedicated port with pads for accessing test data from several on-chip data sources. This port permits a large quantity of internal state data to be sent off the chip at a relatively high bandwidth. Despite the advances offered by this dedicated port, the amount of transmission bandwidth available from this port still reflects but a fraction of the bandwidth required to sample all of the data being generated internally in the chip. Thus, even with the increased bandwidth offered by the dedicated test port, there is a mismatch between the chip's ability to create data and the port's ability to off-load the data. Given this mismatch, it is impossible to get all of the internal state data off the chip.
One way to handle the mismatch between the amount of state data being created and the output data rate has been through selection of the data to be output. The prior art systems that have attempted to address this problem have been configured to operate in a worst case scenario, so that if the output port is saturated, some fraction of the data, or the most desirable data, will be selected and sent off chip. Thus, as example, the operator may configure the device to output every n
th
packet of data, and discard all others. Alternatively, the device may be configured to ignore all non-operational packets, and send only operational packets off chip. The problem with these approaches is there are periods when the output port is not saturated, and therefore other internal state data could be sent off-chip during these periods. Unfortunately, no one has developed a system that permits internal state data to be off-loaded in dynamic fashion, so that the most important data is off-loaded during periods when the port is saturated, and all state data is off-loaded if the port is not saturated.
It would be desirable if a system or technique was developed that would permit the downloading of data from a device under test to external logic analyzers, while operating the device at normal or c
Hewlett--Packard Development Company, L.P.
Lamarre Guy J.
Trimmings John P
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