Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2005-05-13
2010-10-12
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
07814402
ABSTRACT:
An architecture and a method are provided for decoding codewords for codes such as low density parity check (LDPC) codes. An iterative decoding algorithm such as the Belief Propagation Algorithm (BPA) is employed that attempts to correct errors in an input block of symbols via a structure containing two sets of nodes through node processing and the passing of messages between nodes. Message passing and node processing is performed in a digit-serial manner instead of a bit-parallel manner.
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Wang et al., Graph based iterative decoding algorithm for parity concatenated terllis codes, Mar. 2001, IEEE Trans on Info Theory vol. 47, No. 3, p. 1062 to 1074.
Hemati et al., Iterative decoding in analog CMOS, Apr. 2003, GLSVLSI, ACM, (retrived from google.com Jun. 4, 2010), p. 15 to 20.
“A Bit-Serial Approximate Min-Sum LDPC Decoder and FPGA Implementation”; Ahmad Darabiha, Anthony Chan Carusone and Frank R. Kschischang; IEEE 2006; pp. 149-152.
Bates Stephen
Cockburn Bruce Fordyce
Gaudet Vincent
Goud Paul Andrew
Hang Robert
Chase Shelly A
Gordon & Jacobson, PC
The Governors of The University of Alberta
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